YGV629
z
Pattern Memory Interface
No.
1
2
3
4
5
6
7
8
Items
Symbol
tdMA
tdOE
tdWE
tsMD
Min.
Typ.
Max. Unit Note
MA24-0 : output delay time from SYCLK
MOE_N : output delay time from SYCLK
MWE_N : output delay time from SYCLK
MD15-0 : input setup time to SYCLK
MD15-0 : input hold time from SYCLK
MD15-0 : output delay time from SYCLK
MA24-0 : hold time from MOE_N
16
11
11
1
1
1
1
1
1
2
2
4
0
thMD
tdMD
24
ns
thMAR
thMDI
thMAW
thMDO
toffMDO
ton/offRA
0
0
1
1
1
MD15-0 : input hold time from MOE_N, MA
MA24-0 : hold time from MWE_N
9
10 MD15-0 : hold time from MWE_N
11 MD15-0 : turn off time from MWE_N
12 Output turn off/on time from /RAHZ
Note1) SYCLK is an internal clock.
6
25
・Memory Access Cycle (Random Read Cycle)
SYCLK
1
1
MA24-0
MOE_N
MWE_N
MD15-0
2
2
7
3
8
4
5
・Memory Access Cycle (Write Cycle)
SYCLK
1
1
MA24-0
MOE_N
MWE_N
MD15-0
2
9
3
3
11
10
6
-21-
4GV629A50