YGV629
z
AC Characteristics
Measurement Conditions
・Input Voltage: 0V to VDD
・Input Transition Time: 1ns (Transition time is regulated between VDD×0.2 and VDD×0.8)
・Measurement Reference Voltage: Input VIL or VIH
Output VDD×0.5 [V]
・Output Load Capacitance: 20pF
z
Clock Input
No.
Items
Symbol
fXIN
tXIN
fDTCKIN
tDTCKIN
twhCLK
twlCLK
tSYCLK
tDCLK
Min.
6
25
Typ.
Max.
40
166
40
Unit Note
MHz
ns
MHz
ns
ns
XIN Input Clock Frequency
XIN Clock Cycle Time
1
2
DTCKIN Input Clock Frequency
DTCKIN Clock Cycle Time
XIN, DTCKIN Clock High Level Pulse Width
XIN, DTCKIN Clock Low Level Pulse Width
SYCLK(PLL Out) Clock Cycle Time
DCLK Clock Cycle Time
25
7.5
7.5
12.5
25
3
4
5
6
ns
16.6
ns
ns
1
2
Note1) SYCLK is an internal clock generated in the PLL. tSYCLK is a regulation to the value that is found by the
following formula, to the input clock to XIN pin.
tSYCLK = tXIN × k ÷ n (1 ≤ k ≤ 4, 1 ≤ n ≤ 16)
Note2) DCLK is a Dot Clock that is used inside.
1, 2
3
4
VIH
VDD x 0.5
VIL
-16-
4GV629A50
YAMAHA [ YAMAHA CORPORATION ]
