R
QPRO XQ4000E/EX QML High-Reliability FPGAs
Bound
Bound
Scan
Pin Description
PG191 CB196
Pin Description
PG191 CB196
Scan
370
-
I/O
H16
H17
H18
J18
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
P100
P101
286
291
295
298
301
304
-
PGCK3_(I/O)
-
U16
-
P102
(1)
I/O
P103
P104
P105
P106
P107
P108
P109
P110
P111
P112
P113
P114
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
I/O
I/O
T14
U15
V17
V16
T13
U14
V15
V14
T12
U13
V13
U12
V12
T11
U11
V11
V1
376
376
379
382
385
388
391
394
-
I/O
I/O
I/O
J17
I/O_(D6)
I/O
I/O_(/ERR_/INIT)
J16
VCC
GND
I/O
J15
I/O
K15
K16
K17
K18
L18
L17
L16
M18
M17
N18
P18
M16
N17
R18
T18
P17
N16
T17
R17
P16
U18
T16
R16
U17
R15
V18
T15
-
I/O
307
310
313
316
319
322
325
328
331
334
-
I/O
I/O
I/O
I/O
GND
I/O
I/O
397
400
403
406
409
412
415
418
421
424
-
I/O
I/O
I/O
I/O_(D5)
I/O_(/CSO)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
337
340
343
349
349
352
355
358
361
364
-
I/O_(D4)
I/O
U10
T10
R10
R9
I/O
I/O
VCC
GND
I/O_(D3)
I/O_(/RS)
I/O
I/O
-
I/O
T9
427
430
433
436
439
442
445
448
451
454
-
I/O
U9
I/O
V9
I/O
I/O
V8
I/O
I/O
U8
SGCK3_(I/O)
GND
DONE
VCC
/PROG
I/O_(D7)
I/O
T8
I/O_(D2)
I/O
V7
-
U7
-
I/O
V6
-
I/O
U6
367
GND
T7
Notes:
1. Indicates unconnected package pins.
Notes:
1. Indicates unconnected package pins.
2. Contributes only one bit (.I) to the boundary scan register.
Boundary Scan Bit 0 = TD0.T
2. Contributes only one bit (.I) to the boundary scan register.
Boundary Scan Bit 0 = TD0.T
Boundary Scan Bit 1 = TD0.0
Boundary Scan Bit 1 = TD0.0
Boundary Scan Bit 487 = BSCAN.UPD
Boundary Scan Bit 487 = BSCAN.UPD
DS021 (v2.2) June 25, 2000
Product Specification
www.xilinx.com
1-800-255-7778
33
XILINX [ XILINX, INC ]
