R
QPRO XQ4000E/EX QML High-Reliability FPGAs
CB191/196 Package for XQ4010E
Bound
Scan
Pin Description
PG191 CB196
Bound
Scan
I/O
B12
A13
C12
B13
A14
A15
C13
B14
A16
B15
C14
A17
B16
C15
D15
A18
D16
C16
B17
E16
-
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
206
209
-
Pin Description
PG191 CB196
I/O
GND
D4
C3
C4
B3
P1
P2
P3
P4
-
GND
PGCK1_(A16*I/0)
122
125
128
-
I/O
212
215
218
221
224
227
230
233
236
239
242
-
I/O_(A17)
I/0
I/O
I/O
(1)
-
-
P5
I/O
I/O
C5
A2
P6
131
134
137
140
143
146
149
-
I/O
I/O_(TDI)
I/O_(TCK)
I/O
P7
I/O
B4
P8
I/O
C6
A3
P9
I/O
I/O
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
I/O
I/O
B5
SCGK2_(I/O)
I/O
B6
M1
GND
I/O
C7
A4
GND
152
155
158
161
164
167
170
173
176
179
-
(2)
M0
245
I/O
A5
VCC
-
I/O_(TMS)
I/O
B7
(2)
M2
246
A6
PGCK2_(I/O)
247
250
-
I/O
C8
A7
I/O_(HDC)
I/O
(1)
-
I/O
P54
I/O
B8
C17
D17
B18
E17
F16
C18
D18
F17
G16
E18
F18
G17
G18
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
253
256
259
262
265
268
271
274
-
I/O
A8
I/0
I/O
B9
I/O
I/O
C9
D9
D10
C10
B10
A9
I/O_(LDC)
I/O
GND
VCC
I/O
-
I/O
182
185
-
I/O
I/O
I/O
I/O
GND
I/O
I/O
A10
A11
C11
B11
A12
191
194
197
200
203
277
280
283
286
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Notes:
1. Indicates unconnected package pins.
2. Contributes only one bit (.I) to the boundary scan register.
Boundary Scan Bit 0 = TD0.T
Notes:
1. Indicates unconnected package pins.
2. Contributes only one bit (.I) to the boundary scan register.
Boundary Scan Bit 0 = TD0.T
Boundary Scan Bit 1 = TD0.0
Boundary Scan Bit 487 = BSCAN.UPD
Boundary Scan Bit 1 = TD0.0
Boundary Scan Bit 487 = BSCAN.UPD
32
www.xilinx.com
1-800-255-7778
DS021 (v2.2) June 25, 2000
Product Specification
XILINX [ XILINX, INC ]
