R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4028EX IOB Input Switching Characteristic Guidelines (Continued)
-4
Symbol
Description
Min
Units
Setup Times
T
Pad to Clock (IK), no delay
Pad to Clock (IK), partial delay
Pad to Clock (IK), full delay
2.5
10.8
15.7
3.9
ns
ns
ns
ns
ns
ns
ns
PICK
T
T
PICKP
PICKD
T
Pad to Clock (IK), via transparent Fast Capture Latch, no delay
Pad to Clock (IK), via transparent Fast Capture Latch, partial delay
Pad to Fast Capture Latch Enable (OK), no delay
PICKF
T
12.3
0.8
PICKFP
T
POCK
T
Pad to Fast Capture Latch Enable (OK), partial delay
9.1
POCKP
Setup Times (TTL or CMOS Inputs)
T
Clock Enable (EC) to Clock (IK)
0.3
ns
ECIK
Hold Times
T
Pad to Clock (IK), no delay
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
IKPI
T
T
T
Pad to Clock (IK), partial delay
IKPIP
IKPID
IKPIF
Pad to Clock (IK), full delay
Pad to Clock (IK) via transparent Fast Capture Latch, no delay
Pad to Clock (IK) via transparent Fast Capture Latch, partial delay
Pad to Clock (IK) via transparent Fast Capture Latch, full delay
Clock Enable (EC) to Clock (IK), no delay
T
T
IKFPIP
IKFPID
T
IKEC
IKECP
IKECD
T
T
Clock Enable (EC) to Clock (IK), partial delay
Clock Enable (EC) to Clock (IK), full delay
T
Pad to Fast Capture Latch Enable (OK), no delay
Pad to Fast Capture Latch Enable (OK), partial delay
OKPI
T
OKPIP
Notes:
1. For CMOS input levels, see the "XQ4028EX Input Threshold Adjustments" on page 28.
2. For setup and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Setup and Hold
tables on page 28.
30
www.xilinx.com
DS021 (v2.2) June 25, 2000
1-800-255-7778
Product Specification
XILINX [ XILINX, INC ]
