R
Platform Flash In-System Programmable Configuration PROMs
XCFxxP PROM as Configuration Master with CLK Input Pin as Clock Source
X-Ref Target - Figure 8
CE
T
HCE
T
HOE
T
CYCO
T
LC
T
HC
OE/RESET
CLK
T
CLKO
CLKOUT
T
CECC
T
OECC
T
SB
T
HB
T
CCDD
T
COH
T
DDC
T
OE
T
CE
T
CECF
T
OECF
BUSY
(optional)
DATA
T
CF
T
CFCC
T
HCF
T
EOH
T
DF
CF
EN_EXT_SEL
T
SXT
T
HXT
T
SXT
T
HXT
REV_SEL[1:0]
T
SRV
T
HRV
T
SRV
T
HRV
Note:
Typically,
8
CLKOUT cycles
are
output
after
CE rising edge,
before
CLKOUT
tristates, if OE/RESET remains high,
and
terminal count has not
been
reached.
ds123_25_110707
Symbol
Description
CF hold time to guarantee design revision selection is sampled
when V
CCO
= 3.3V or 2.5V
(11)
CF hold time to guarantee design revision selection is sampled
when V
CCO
= 1.8V
(11)
CF to data delay when VCCO = 3.3V or 2.5V
CF to data delay when VCCO = 1.8V
OE/RESET to data delay
(6)
when V
CCO
= 3.3V or 2.5V
OE/RESET to data delay
(6)
when V
CCO
= 1.8V
CE to data delay
(5)
when V
CCO
= 3.3V or 2.5V
CE to data delay
(5)
when V
CCO
= 1.8V
Data hold from CE, OE/RESET, or CF when V
CCO
= 3.3V or 2.5V
Data hold from CE, OE/RESET, or CF when V
CCO
= 1.8V
CE or OE/RESET to data float delay
(2)
when V
CCO
= 3.3V or 2.5V
CE or OE/RESET to data float delay
(2)
when V
CCO
= 1.8V
OE/RESET to CLKOUT float delay
(2)
when V
CCO
= 3.3V or 2.5V
OE/RESET to CLKOUT float delay
(2)
when V
CCO
= 1.8V
CE to CLKOUT float delay
(2)
when V
CCO
= 3.3V or 2.5V
CE to CLKOUT float delay
(2)
when V
CCO
= 1.8V
XCF08P, XCF16P,
XCF32P
Min
300
300
–
–
–
–
–
–
5
5
–
–
–
–
–
–
25
25
25
25
–
–
45
45
Units
Max
300
300
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
T
HCF
T
CF
T
OE
T
CE
T
EOH
T
DF
T
OECF
T
CECF
DS123 (v2.17) October 26, 2009
Product Specification
18
XILINX [ XILINX, INC ]
