R
Platform Flash In-System Programmable Configuration PROMS
Table 12: XCFxxP Pin Names and Descriptions (Continued)
48-pin
TSOP
(VO48/
48-pin
TFBGA
(FS48/
Boundary
Scan
Boundary
Scan
Pin Name
Order
Function
Pin Description
VOG48) FSG48)
Chip Enable Output. Chip Enable Output (CEO) is connected
to the CE input of the next PROM in the chain. This output is
Low when CE is Low and OE/RESET input is High, AND the
internal address counter has been incremented beyond its
Terminal Count (TC) value. CEO returns to High when
OE/RESET goes Low or CE goes High.
06
05
Data Out
CEO
10
25
D2
H4
Output Enable
Enable External Selection Input. When this pin is Low, design
revision selection is controlled by the Revision Select pins.
When this pin is High, design revision selection is controlled
by the internal programmable Revision Select control bits.
EN_EXT_SEL has an internal 50KΩ resistive pull-up to VCCO
to provide a logic "1" to the device if the pin is not driven.
EN_EXT_SEL
31
Data In
Revision Select[1:0] Inputs. When the EN_EXT_SEL is Low,
the Revision Select pins are used to select the design
revision to be enabled, overriding the internal programmable
Revision Select control bits. The Revision Select[1:0] inputs
have an internal 50KΩ resistive pull-up to VCCO to provide a
logic "1" to the device if the pins are not driven.
REV_SEL0
REV_SEL1
30
29
Data In
Data In
26
27
G3
G4
Busy Input. The BUSY input is enabled when parallel mode
is selected for configuration. When BUSY is High, the internal
address counter stops incrementing and the current data
remains on the data pins. On the first rising edge of CLK after
BUSY transitions from High to Low, the data for the next
address is driven on the data pins. When serial mode or
decompression is enabled during device programming, the
BUSY input is disabled. BUSY has an internal 50KΩ resistive
pull-down to GND to provide a logic "0" to the device if the pin
is not driven.
BUSY
12
Data In
5
C1
Configuration Clock Output. An internal Programmable
control bit enables the CLKOUT signal which is sourced from
either the internal oscillator or the CLK input pin. Each rising
edge on the selected clock source increments the internal
address counter if data is available, CE is Low, and
OE/RESET is High. Output data is available on the rising
edge of CLKOUT. CLKOUT remains Low when data is not
ready. When CLKOUT is not enabled , the CLKOUT pin is put
into a high-impedance state.
08
07
Data Out
CLKOUT
9
C2
E2
Output Enable
JTAG Mode Select Input. The state of TMS on the rising edge
of TCK determines the state transitions at the Test Access
Port (TAP) controller. TMS has an internal 50KΩ resistive
pull-up to VCCJ to provide a logic "1" to the device if the pin is
not driven.
TMS
Mode Select
21
JTAG Clock Input. This pin is the JTAG test clock. It
sequences the TAP controller and all the JTAG test and
programming electronics.
TCK
TDI
Clock
20
19
H3
G1
JTAG Serial Data Input. This pin is the serial input to all JTAG
instruction and data registers. TDI has an internal 50KΩ
resistive pull-up to VCCJ to provide a logic "1" to the device if
the pin is not driven.
Data In
JTAG Serial Data Output. This pin is the serial output for all
JTAG instruction and data registers. TDO has an internal
50KΩ resistive pull-up to VCCJ to provide a logic "1" to the
system if the pin is not driven.
TDO
Data Out
22
E6
DS123 (v2.4) July 20, 2004
Preliminary Product Specification
www.xilinx.com
1-800-255-7778
34
XILINX [ XILINX, INC ]
