R
Platform Flash In-System Programmable Configuration PROMS
AC Characteristics Over Operating Conditions When Cascading
OE/RESET
CE
CLK
CLKOUT
(optional)
T
T
CDF
CODF
DATA
CEO
Last Bit
First Bit
T
OCE
T
OOE
T
OCK
T
COCE
ds123_23_102203
XCF01S, XCF02S,
XCF04S
XCF08P, XCF16P,
XCF32P
Symbol
Description
Min
Max
Min
Max
Units
CLK to output float delay(2,3)
when VCCO = 2.5V or 3.3V
-
25
TBD
TBD
ns
TCDF
CLK to output float delay(2,3) when VCCO = 1.8V
-
-
-
-
-
-
-
-
-
35
20
35
20
35
20
35
-
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK to CEO delay(3,5) when VCCO = 2.5V or 3.3V
CLK to CEO delay(3,5) when VCCO = 1.8V
TOCK
TOCE
TOOE
TCOCE
CE to CEO delay(3) when VCCO = 2.5V or 3.3V
CE to CEO delay(3) when VCCO = 1.8V
OE/RESET to CEO delay(3) when VCCO = 2.5V or 3.3V
OE/RESET to CEO delay(3) when VCCO = 1.8V
CLKOUT to CEO delay when VCCO = 2.5V or 3.3V
CLKOUT to CEO delay when VCCO = 1.8V
-
CLKOUT to output float delay
when VCCO = 2.5V or 3.3V
-
-
-
-
TBD
TBD
TBD
TBD
ns
ns
TCODF
CLKOUT to output float delay when VCCO = 1.8V
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
5. For cascaded PROMs:
- TCYC min = TOCK + TCE + FPGA data setup time
- TCAC min = TOCK + TCE
DS123 (v2.4) July 20, 2004
www.xilinx.com
30
Preliminary Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
