R
Platform Flash In-System Programmable Configuration PROMS
XCFxxP Pinouts and Pin Descriptions
Table 12 provides a list of the pin names and descriptions for the XCFxxP 48-pin VO48/VOG48 and 48-pin FS48/FSG48
packages.
Table 12: XCFxxP Pin Names and Descriptions
48-pin
TSOP
(VO48/
48-pin
TFBGA
(FS48/
Boundary
Scan
Boundary
Scan
Pin Name
D0
Order
Function
Pin Description
VOG48) FSG48)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
Data Out
Output Enable
Data Out
28
29
32
33
43
44
47
48
H6
H5
E5
D5
C5
B5
A5
A6
D1
D2
D3
D4
D5
D6
D7
Output Enable
Data Out
D0 is the DATA output pin to provide data for configuring an
FPGA in serial mode.
Output Enable
Data Out
D0-D7 are the DATA output pins to provide parallel data for
configuring a Xilinx FPGA in SelectMap (parallel) mode.
Output Enable
Data Out
The D0 output is set to a high-impedance state during ISPEN
(when not clamped).
The D1-D7 outputs are set to a high-impedance state during
ISPEN (when not clamped) and when serial mode is selected
for configuration. The D1-D7 pins can be left unconnected
when the PROM is used in serial mode.
Output Enable
Data Out
Output Enable
Data Out
Output Enable
Data Out
Output Enable
Configuration Clock Input. An internal programmable control
bit selects between the internal oscillator and the CLK input
pin as the clock source to control the configuration sequence.
Each rising edge on the CLK input increments the internal
address counter if the CLK input is selected, CE is Low,
OE/RESET is High, BUSY is Low (parallel mode only), and
CF is High.
CLK
01
Data In
12
B3
Output Enable/Reset (Open-Drain I/O).
04
03
02
Data In
Data Out
When Low, this input holds the address counter reset and the
DATA and CLKOUT outputs are placed in a high-impedance
state. This is a bidirectional open-drain pin that is held Low
while the PROM is reset. Polarity is not programmable.
OE/RESET
CE
11
13
A3
B4
Output Enable
Chip Enable Input. When CE is High, the device is put into
low-power standby mode, the address counter is reset, and
the DATA and CLKOUT outputs are placed in a
high-impedance state.
00
Data In
Configuration Pulse (Open-Drain I/O). As an output, this pin
allows JTAG CONFIG instruction to initiate FPGA
configuration without powering down the FPGA. This is an
open-drain signal that is pulsed Low by the JTAG CONFIG
command. As an input, when Low, this signal resets the
internal address counter. The current design revision
selection is sampled on the rising edge of CF.
11
10
09
Data In
Data Out
CF
6
D1
Output Enable
DS123 (v2.4) July 20, 2004
Preliminary Product Specification
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XILINX [ XILINX, INC ]
