Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics
Table 6: Power-On Current for Artix-7 Devices (Cont’d)
Device
XQ7A100T
XQ7A200T
ICCINTMIN
ICCAUXMIN
ICCAUXQ + 40
ICCAUXQ + 50
ICCOMIN
ICCBRAMMIN
ICCBRAMQ + 60
ICCBRAMQ + 80
Units
mA
ICCINTQ + 170
ICCOQ + 40 mA per bank
ICCOQ + 40 mA per bank
I
CCINTQ + 340
mA
Table 7: Power Supply Ramp Time
Symbol
Description
Conditions
Min
0.2
0.2
0.2
0.2
–
Max
50
Units
ms
TVCCINT
TVCCO
TVCCAUX
TVCCBRAM
Ramp time from GND to 90ꢀ of VCCINT
Ramp time from GND to 90ꢀ of VCCO
Ramp time from GND to 90ꢀ of VCCAUX
Ramp time from GND to 90ꢀ of VCCBRAM
50
ms
50
ms
50
ms
TJ = 125°C(1)
300
500
800
50
TVCCO2VCCAUX
Allowed time per power cycle for VCCO – VCCAUX > 2.625V
TJ = 100°C(1)
TJ = 85°C(1)
–
ms
–
TMGTAVCC
TMGTAVTT
Ramp time from GND to 90ꢀ of VMGTAVCC
Ramp time from GND to 90ꢀ of VMGTAVTT
0.2
0.2
ms
ms
50
Notes:
1. Based on 240,000 power cycles with nominal V
of 3.3V or 36,500 power cycles with worst case V
of 3.465V.
CCO
CCO
DC Input and Output Levels
Values for V and V are recommended input voltages. Values for I and I are guaranteed over the recommended
IL
IH
OL
OH
operating conditions at the V and V test points. Only selected standards are tested. These are chosen to ensure that all
OL
OH
standards meet their specifications. The selected standards are tested at a minimum V
voltage levels shown. Other standards are sample tested.
with the respective V and V
CCO
OL OH
(1)(2)
Table 8: SelectIO DC Input and Output Levels
VIL
V, Max
VIH
VOL
V, Max
0.400
0.400
0.400
0.400
VOH
IOL
IOH
I/O Standard
V, Min
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.300
–0.400
–0.300
–0.300
–0.300
V, Min
V, Max
V, Min
mA, Max mA, Min
HSTL_I
VREF – 0.100
VREF – 0.100
VREF – 0.100
VREF – 0.100
VREF + 0.100 VCCO + 0.300
VREF + 0.100 VCCO + 0.300
VREF + 0.100 VCCO + 0.300
VREF + 0.100 VCCO + 0.300
VREF + 0.130 VCCO + 0.300
VCCO – 0.400
VCCO – 0.400
VCCO – 0.400
VCCO – 0.400
80ꢀ VCCO
VCCO – 0.400
75ꢀ VCCO
VCCO – 0.450
VCCO – 0.400
VCCO – 0.400
2.400
8.00
8.00
–8.00
–8.00
HSTL_I_18
HSTL_II
16.00
16.00
0.10
–16.00
–16.00
–0.10
HSTL_II_18
HSUL_12
V
REF – 0.130
20ꢀ VCCO
0.400
LVCMOS12
LVCMOS15
LVCMOS18
LVCMOS25
LVCMOS33
LVTTL
35ꢀ VCCO
35ꢀ VCCO
35ꢀ VCCO
0.7
65ꢀ VCCO
65ꢀ VCCO
65ꢀ VCCO
1.700
VCCO + 0.300
VCCO + 0.300
VCCO + 0.300
VCCO + 0.300
3.450
Note 3
Note 4
Note 5
Note 4
Note 4
Note 5
0.10
Note 3
Note 4
Note 5
Note 4
Note 4
Note 5
–0.10
25ꢀ VCCO
0.450
0.400
0.8
2.000
0.400
0.8
2.000
3.450
0.400
MOBILE_DDR
PCI33_3
20ꢀ VCCO
30ꢀ VCCO
80ꢀ VCCO
50ꢀ VCCO
VCCO + 0.300
VCCO + 0.500
10ꢀ VCCO
10ꢀ VCCO
90ꢀ VCCO
90ꢀ VCCO
1.50
–0.50
SSTL135
V
REF – 0.090
VREF – 0.090
VREF – 0.100
VREF + 0.090 VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150 13.00
VREF + 0.090 VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150 8.90
VREF + 0.100 VCCO + 0.300 VCCO/2 – 0.175 VCCO/2 + 0.175 13.00
–13.00
–8.90
SSTL135_R
SSTL15
–13.00
DS181 (v1.25) June 18, 2018
www.xilinx.com
Product Specification
9
XILINX [ XILINX, INC ]
