Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 70: Clock-Capable Clock Input Setup and Hold With MMCM
Speed Grade
Symbol
Description
Device
Units
-3
-2
-1
-1L
Input Setup and Hold Time Relative to Clock-capable Clock Input Signal for LVCMOS25 Standard.(1)
TPSMMCMCC
/
No Delay Clock-capable Clock Input and XC6VLX75T
IFF(2) with MMCM
1.56/
–0.25
1.69/
–0.25
1.86/
–0.25
1.91/
–0.15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TPHMMCMCC
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T
XC6VLX760
1.64/
–0.25
1.78/
–0.25
1.95/
–0.25
2.00/
–0.14
1.65/
–0.24
1.79/
–0.24
1.96/
–0.24
2.01/
–0.15
1.65/
–0.24
1.79/
–0.24
1.96/
–0.24
2.01/
–0.15
1.66/
–0.25
1.79/
–0.25
1.97/
–0.25
2.02/
–0.15
N/A
1.97/
–0.24
2.16/
–0.24
2.19/
–0.14
N/A
2.39/
–0.20
2.63/
–0.20
2.21/
–0.10
XC6VSX315T
XC6VSX475T
XC6VHX250T
XC6VHX255T
XC6VHX380T
XC6VHX565T
XQ6VLX130T
XQ6VLX240T
XQ6VLX550T
XQ6VSX315T
XQ6VSX475T
1.67/
–0.25
1.80/
–0.25
1.98/
–0.25
2.03/
–0.16
N/A
1.98/
–0.29
2.17/
–0.29
2.21/
–0.20
1.63/
–0.24
1.76/
–0.24
1.94/
–0.24
N/A
N/A
N/A
N/A
1.63/
–0.19
1.76/
–0.19
1.99/
–0.19
1.80/
–0.23
1.94/
–0.23
2.13/
–0.23
N/A
N/A
N/A
N/A
N/A
N/A
1.94/
–0.08
2.13/
–0.08
1.78/
–0.25
1.95/
–0.25
2.00/
–0.14
1.79/
–0.24
1.96/
–0.24
2.01/
–0.15
N/A
2.16/
–0.24
2.19/
–0.14
1.80/
–0.25
1.98/
–0.25
2.03/
–0.16
N/A
2.17/
2.21/
–0.29
–0.20
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS152 (v3.6) March 18, 2014
www.xilinx.com
Product Specification
59
XILINX [ XILINX, INC ]
