Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Description of Revisions
Date
Version
01/18/2010
2.1
Changed absolute maximum ratings for both VIN and VTS in Table 1. Added data to Table 3. Added
data to Table 5. Updated SSTL15 in Table 7. Updated VOCM and VOD values in Table 8. Added eFUSE
endurance Table 12. Added values to VMGTREFCLK and VIN in Table 13, page 11. Added values and
updated tables in the GTX Transceiver Specifications and GTH Transceiver Specifications sections.
Added Table 27 and Figure 4. Revised parameters and values in Table 39. Updated Table 40, page 23.
Added data to Table 41. Updated speed specification to v1.04 with appropriate changes to Table 42
and Table 43 including production release of the XC6VLX240T for -1 and -2 speed grades. Speed
specification changes and numerous updates also made to Table 44, and Table 49 through Table 71.
Added data to Table 73 and Table 74.
02/09/2010
04/12/2010
2.2
2.3
Revised description of CIN in Table 3. Clarified values in Table 5. Fixed SDR LVDS unit error in
Table 41.
Added note 3 and update value of n in Table 3. Clarified simultaneous power-down in Power-On Power
Supply Requirements. Updated external reference junction temperatures in Table 40, Analog-to-Digital
Specifications. Updated speed specification to v1.05 with appropriate changes to Table 42 and
Table 43 including production release of the XC6VLX130T for -1 and -2 speed grades. Fixed note 4 in
Table 48. Increased the -2 specification for FIDELAYCTRL_REF and clarified units for TIDELAYPAT_JIT in
Table 53. Added note 1 to Table 62.
05/11/2010
05/26/2010
2.4
2.5
Updated FRXREC in Table 22. Revised FIDELAYCTRL_REF in Table 53. Removed TRCKO_PARITY_ECC:
Clock CLK to ECCPARITY in standard ECC mode row in Table 57. Added XC6VLX130T values to
Table 72.
Added XC6VLX195T data to Table 5. Updated values in Table 22 including adding note 2 and note 3.
Updated speed specification to v1.06 with appropriate changes to Table 42 and Table 43 including
production release of the XC6VLX195T for -1 and -2 speed grades. Added XC6VLX195T values to
Table 72.
07/16/2010
07/23/2010
2.6
2.7
Changed Table 42 and Table 43 to production status on the -3 speed grade XC6VLX130T,
XC6VLX195T, and XC6VLX240T devices. Added XC6VHX250Tdata to Table 4 and Table 72. Added
Note 6 to Table 64.
Changed Table 42 and Table 43 to production status on the XC6VLX75T, XC6VLX365T, XC6VLX550T,
XC6VLX760, XC6VSX315T, and XC6VSX475T devices using ISE 12.2 software with speed
specification v1.08. Updated VCMOUTDC equation to MGTAVTT – DVPPOUT/4 in Table 17. Updated
some -3, -2, -1 specifications in Table 65 through Table 72. Added and updated -1L specifications to
Table 41 and for most switching characteristics tables.
07/30/2010
2.8
Changed Table 42 and Table 43 to production status on the -1L speed grade for the XC6VLX130T,
XC6VLX195T, XC6VLX240T, XC6VLX365T, and XC6VLX550T devices using ISE 12.2 software with
current speed specifications. Also updated the speed specifications for XC6VLX75T, XC6VLX550T,
and XC6VSX315T. Updated VCCINT specifications for -1L speed grade industrial temperature range
devices in Table 2.
09/20/2010
10/18/2010
2.9
In Table 32, changed FGPLLMAX specification in -3 column from 5.951 to 5.591. In Table 40, changed
F
MAX for the DCLK from 250 MHz to 80 MHz.
2.10
The specification change in version 2.9, Table 40 is described in XCN10032, Virtex-6 FPGA: GTX
Transceiver User Guide, Family Data Sheet (SYSMON DCLK), and JTAG ID Changes
In this version (2.10), -1L(I) data is added to Table 4 and clarified in Note 2. Changed Table 42 and
Table 43 to production status on the -1L speed grade XC6VLX75T, XC6VLX760, XC6VSX315T, and
XC6VSX475T devices using ISE 12.3 software with current speed specifications. Revised the
XC6VLX760 -1L speed specification for TPHMMCMGC in Table 69 and TPHMMCMCC in Table 70.
01/17/2011
2.11
Changed in Table 42 and Table 43 to production status on the XC6VHX250T devices using ISE 12.4
software with current speed specifications.
Added industrial temperature range (Tj) recommended specifications to Table 2; including specific
ranges for the -2I XC6VSX475T, XC6VLX550T, XC6VLX760, and XC6VHX565Tdevices. Added
note 3 to Table 36 and maximum total jitter values. Added note 4 to Table 37 and maximum sinusoidal
jitter values. Added note 2 to Table 43. Revised FMAX descriptions in Table 57 and added note 12.
Added note 8 to FPFDMIN in Table 64.
The following revisions are due to specification changes as described in XCN11009, Virtex-6 FPGA:
Data Sheet, User Guides, and JTAG ID Updates.
In Table 59:Configuration Switching Characteristics, page 49, revised -1L specifications for TPOR
MCCK, FMCCKTOL, TSMCSCCK, TSMCCKW, FRBCCK, FTCK, FTCKB, TMCCKL, and TMCCKH. In Table 64:
MMCM Specification, added bandwidth settings to FPFDMIN and added note 1.
,
F
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