Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 54: CLB Switching Characteristics (Cont’d)
Speed Grade
Units
Symbol
Description
-3
-2
-1
-1L
TITO
An – Dn inputs to A – D Q outputs
AX inputs to AMUX output
AX inputs to BMUX output
AX inputs to CMUX output
AX inputs to DMUX output
BX inputs to BMUX output
BX inputs to DMUX output
CX inputs to CMUX output
CX inputs to DMUX output
DX inputs to DMUX output
An input to COUT output
Bn input to COUT output
Cn input to COUT output
Dn input to COUT output
AX input to COUT output
BX input to COUT output
CX input to COUT output
DX input to COUT output
CIN input to COUT output
CIN input to AMUX output
CIN input to BMUX output
CIN input to CMUX output
CIN input to DMUX output
0.59
0.31
0.35
0.39
0.42
0.30
0.38
0.26
0.30
0.30
0.32
0.32
0.27
0.25
0.25
0.22
0.15
0.14
0.06
0.21
0.23
0.23
0.25
0.67
0.35
0.39
0.44
0.47
0.34
0.43
0.29
0.34
0.33
0.36
0.36
0.30
0.28
0.28
0.24
0.17
0.16
0.07
0.24
0.25
0.26
0.29
0.79
0.42
0.47
0.52
0.55
0.39
0.50
0.34
0.40
0.38
0.41
0.41
0.34
0.32
0.33
0.28
0.20
0.19
0.08
0.28
0.29
0.30
0.33
0.85
0.44
0.50
0.56
0.60
0.44
0.55
0.37
0.44
0.43
0.47
0.47
0.40
0.37
0.36
0.31
0.22
0.21
0.09
0.30
0.31
0.33
0.36
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
TAXA
TAXB
TAXC
TAXD
TBXB
TBXD
TCXC
TCXD
TDXD
TOPCYA
TOPCYB
TOPCYC
TOPCYD
TAXCY
TBXCY
TCXCY
TDXCY
TBYP
TCINA
TCINB
TCINC
TCIND
Sequential Delays
TCKO
Clock to AQ – DQ outputs
0.29
0.36
0.33
0.40
0.39
0.47
0.44
0.53
ns, Max
ns, Max
TSHCKO
Clock to AMUX – DMUX outputs
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
T
DICK/TCKDI
A – D input to CLK on A – D Flip Flops
CE input to CLK on A – D Flip Flops
0.30/0.17 0.36/0.18 0.43/0.20 0.44/0.25
0.20/0.00 0.25/0.00 0.32/0.00 0.32/0.01
ns, Min
ns, Min
TCECK_CLB
/
TCKCE_CLB
TSRCK/TCKSR
CINCK/TCKCIN
SR input to CLK on A – D Flip Flops
CIN input to CLK on A – D Flip Flops
0.39/–0.07 0.44/–0.07 0.52/–0.07 0.58/–0.08
0.16/0.12 0.19/0.14 0.24/0.16 0.23/0.22
ns, Min
ns, Min
T
Set/Reset
TSRMIN
TRQ
SR input minimum pulse width
0.90
0.52
0.90
0.58
0.97
0.68
0.80
0.77
ns, Min
ns, Max
ns, Max
MHz
Delay from SR input to AQ – DQ flip-flops
Delay from CE input to AQ – DQ flip-flops
Toggle frequency (for export control)
TCEO
0.41
0.48
0.59
0.61
FTOG
1412.00
1286.40
1098.00
1098.00
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
2. These items are of interest for Carry Chain applications.
DS152 (v3.6) March 18, 2014
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