Pinout Descriptions
FT256 Footprint (XC3S700A, XC3S1400A)
Bank 0
11
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND PROG_B
GND
TCK
L12P_0 L10N_0
GCLK10
A
B
C
D
E
F
L19P_0 L18P_0 L17P_0 L15P_0 L13P_0
L08N_0 L07N_0 L05N_0 L04N_0 L04P_0
GCLK7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TDI
I/O
TMS
I/O
VCCO_0
I/O
GND L12N_0 VCCO_0
GND
I/O
VCCO_0
I/O
L02P_0
VREF_0
TDO
I/O
L19N_0 L18N_0
L15N_0
L08P_0
L05P_0
L02N_0
GCLK11
I/O
L20P_0
VREF_0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
L11P_0 L10P_0 L09P_0
GCLK8 GCLK6 GCLK4
GND
I/O
L24N_1 L24P_1
L01N_3 L01P_3
L17N_0 L16N_0 L13N_0
L07P_0 L03P_0 L01N_0
A25
A24
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L16P_0
I/O
I/O
I/O
VCCO_3
L03P_3
L20N_0 VCCAUX
L11N_0 L09N_0 L06N_0
GCLK9 GCLK5 VREF_0
L23N_1 L22N_1 L22P_1
L02N_3 L02P_3
L06P_0 L03N_0 L01P_0
PUDC_B
A23
A21
A20
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L14P_0
GND
INPUT L14N_0 VCCO_0
GND VCCAUX GND
L23P_1 L20P_1 VCCO_1 L18P_1
L03N_3 L05N_3 L05P_3 L04P_3
VREF_0
A22
A18
A14
I/O
I/O
I/O
I/O
I/O
L08P_3
I/O
I/O
GND
I/O
VCCAUX GND
GND
GND
GND
GND VCCINT GND VCCAUX L20N_1 L19N_1 L18N_1 L16N_1
L07P_3 L04N_3
A19
A17
A15
A11
I/O
I/O
I/O
I/O
L16P_1
A10
I/O
L07N_3
INPUT
VREF_3
L08N_3 L11P_3
VREF_3 LHCLK0
GND
GND
VCCINT
VCCINT
GND
VCCINT GND
INPUT
L19P_1 L17N_1
GND
G
H
J
A16
A13
I/O
I/O
I/O
I/O
I/O
L15N_1
RHCLK7
L15P_1
IRDY1
RHCLK6
L11N_3 VCCO_3 L12P_3 VCCAUX GND VCCINT GND VCCINT GND VCCINT GND
L17P_1 VCCAUX
A12
VREF_1
LHCLK1
LHCLK2
I/O
I/O
I/O
I/O
I/O
I/O
INPUT
VREF_3
INPUT
VREF_1
L12N_3
IRDY2
LHCLK3
L12N_1
TRDY1
RHCLK3
L14N_3 L14P_3
LHCLK5 LHCLK4
INPUT
GND
VCCINT
GND
VCCINT
GND
VCCINT L10P_1 L10N_1
VCCO_1
A8
A9
I/O
I/O
L15N_3
LHCLK7
I/O
I/O
I/O
I/O
I/O
L18P_3
L15P_3
TRDY2
LHCLK6
GND
GND VCCINT GND VCCINT GND VCCINT GND
GND
L06N_1 L11N_1 L11P_1 L12P_1
K
L
A3
RHCLK1 RHCLK0 RHCLK2
I/O
I/O
I/O
I/O
L08N_1
A7
I/O
I/O
I/O
L16P_3
VREF_3
VCCAUX GND
GND VCCAUX
VCCINT
GND
VCCINT
GND
VCCAUX
GND
GND VCCAUX L06P_1 L08P_1
GND
I/O
L16N_3 L18N_3 L19N_3
A2
A6
I/O
I/O
L20P_3
I/O
I/O
INPUT
VREF_2
INPUT
VREF_2
INPUT
INPUT INPUT
VREF_1 VREF_1
VCCO_3
GND
I/O
L08N_2 L11P_2
D4
GND
I/O
L07P_1 L07N_1
M
N
P
R
T
L19P_3 L24N_3
VREF_2
A4
A5
I/O
L22P_3
VREF_3
I/O
I/O
I/O
INPUT
I/O
I/O
I/O
I/O
I/O
L20N_3
I/O
L01P_2
L24P_3
M1
L04P_2
GND
I/O
L01P_1 L01N_1 VCCO_1 L03N_1
VREF_2
VS1
L16N_2 L19P_2
GCLK0
HDC
LDC2
GND
I/O
A1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L19N_2
I/O
I/O
INPUT
L14N_2
MOSI
GND
I/O
L01N_2 L04N_2
L08P_2 L10P_2 L11N_2
D5
L17N_2
L16P_2
D3
L02N_1 L03P_1
L22N_3 L23N_3
VREF_2
VS0
M0
GCLK14 GCLK1
LDC0
A0
CSI_B
I/O
I/O
L23P_3
I/O
I/O
I/O
I/O
I/O
I/O
L05N_2
L02P_2 L03P_2 VCCO_2
M2
GND
L09P_2 VCCO_2 L12P_2
GND
L15N_2 VCCO_2 L18N_2 L20N_2 L02P_1
RDWR_B
GCLK12
GCLK2
DOUT
D1
CCLK
LDC1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
L14P_2
I/O
L05P_2
L20P_2
D0/DIN
MISO
GND
L02N_2 L03N_2
L06P_2 L06N_2 L09N_2 L10N_2 L12N_2
L15P_2 L17P_2 L18P_2
DONE
GND
CSO_B
VS2
D7
D6
GCLK13 GCLK15 GCLK3
AWAKE INIT_B
D2
Bank 2
DS529-4_012009
Figure 22: XC3S700A and XC3S1400A FT256 Package Footprint (Top View)
I/O: Unrestricted,
DUAL: Configuration, then
VREF: User I/O or input
SUSPEND: Dedicated
SUSPEND and
dual-purpose AWAKE
Power Management pins
2
59
2
51
30
4
18
13
15
10
general-purpose user I/O
possible user I/O
voltage reference for bank
INPUT: Unrestricted,
general-purpose input pin
CLK: User I/O, input, or
global buffer input
VCCO: Output voltage
supply for bank
CONFIG: Dedicated
configuration pins
JTAG: Dedicated JTAG
port pins
VCCINT: Internal core
supply voltage (+1.2V)
2
N.C.: Not connected
GND: Ground
VCCAUX: Auxiliary supply
voltage
0
50
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
93
XILINX [ XILINX, INC ]
