Pinout Descriptions
FG320: 320-ball Fine-pitch Ball Grid Array
The 320-ball fine-pitch ball grid array package, FG320,
supports two Spartan-3A FPGAs, the XC3S200A and the
XC3S400A, as shown in Table 77 and Figure 23.
Table 77: Spartan-3A FG320 Pinout(Continued)
FG320
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Name
IO_L09P_0
Ball
B11
D10
C11
C9
B10
B9
Type
I/O
The FG320 package is an 18 x 18 array of solder balls
minus the four center balls.
IO_L10N_0
I/O
Table 77 lists all the package pins. They are sorted by bank
number and then by pin name of the largest device. Pins
that form a differential I/O pair appear together in the table.
The table also shows the pin number for each pin and the
pin type, as defined earlier.
IO_L10P_0
I/O
IO_L11N_0/GCLK5
IO_L11P_0/GCLK4
IO_L12N_0/GCLK7
IO_L12P_0/GCLK6
IO_L13N_0/GCLK9
IO_L13P_0/GCLK8
IO_L14N_0/GCLK11
IO_L14P_0/GCLK10
IO_L15N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
The shaded rows indicate pinout differences between the
XC3S200A and the XC3S400A FPGAs. The XC3S200A
has three unconnected balls, indicated as N.C. (No
Connection) in Table 77 and with the black diamond
character () in Table 77 and Figure 23.
A10
B7
A8
C8
B8
All other balls have nearly identical functionality on all three
devices. Table 80 summarizes the Spartan-3A FPGA
footprint migration differences for the FG320 package.
C7
D8
E9
IO_L15P_0
I/O
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at
IO_L16N_0
I/O
IO_L16P_0
D9
B6
I/O
IO_L17N_0
I/O
www.xilinx.com/support/documentation/data_sheets/
s3a_pin.zip.
IO_L17P_0
A6
I/O
IO_L18N_0/VREF_0
IO_L18P_0
A4
VREF
I/O
Pinout Table
A5
Table 77: Spartan-3A FG320 Pinout
IO_L19N_0
E7
I/O
IO_L19P_0
F8
I/O
FG320
Bank
Pin Name
IO_L01N_0
Ball
C15
C16
A16
B16
A14
A15
C14
B15
D12
C13
A13
B13
B12
C12
F11
E11
A11
Type
I/O
IO_L20N_0
D6
C6
A3
I/O
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO_L20P_0
I/O
IO_L01P_0
I/O
IO_L21N_0
I/O
IO_L02N_0
IO_L02P_0/VREF_0
IO_L03N_0
IO_L03P_0
I/O
IO_L21P_0
B4
I/O
VREF
I/O
IO_L22N_0
D5
C5
A2
I/O
IO_L22P_0
I/O
I/O
IO_L23N_0
I/O
IO_L04N_0
IO_L04P_0
I/O
IO_L23P_0
B3
I/O
I/O
IO_L24N_0/PUDC_B
IO_L24P_0/VREF_0
IP_0
E5
DUAL
VREF
INPUT
INPUT
INPUT
IO_L05N_0
IO_L05P_0
I/O
E6
I/O
D13
D14
E12
IO_L06N_0/VREF_0
IO_L06P_0
VREF
I/O
IP_0
IP_0
IO_L07N_0
IO_L07P_0
I/O
XC3S400A: IP_0
XC3S200A: N.C. (◆)
0
E13
INPUT
I/O
0
0
0
IP_0
IP_0
IP_0
F7
F9
INPUT
INPUT
INPUT
IO_L08N_0
IO_L08P_0
I/O
I/O
F10
IO_L09N_0
I/O
94
www.xilinx.com
DS529-4 (v2.0) August 19, 2010
XILINX [ XILINX, INC ]
