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XC3S200A-4FTG256C 参数 Datasheet PDF下载

XC3S200A-4FTG256C图片预览
型号: XC3S200A-4FTG256C
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 448 CLBs, 200000 Gates, 250MHz, 4032-Cell, CMOS, PBGA256, LEAD FREE, FPTBGA-256]
分类和应用: 时钟可编程逻辑
文件页数/大小: 132 页 / 3936 K
品牌: XILINX [ XILINX, INC ]
 浏览型号XC3S200A-4FTG256C的Datasheet PDF文件第84页浏览型号XC3S200A-4FTG256C的Datasheet PDF文件第85页浏览型号XC3S200A-4FTG256C的Datasheet PDF文件第86页浏览型号XC3S200A-4FTG256C的Datasheet PDF文件第87页浏览型号XC3S200A-4FTG256C的Datasheet PDF文件第89页浏览型号XC3S200A-4FTG256C的Datasheet PDF文件第90页浏览型号XC3S200A-4FTG256C的Datasheet PDF文件第91页浏览型号XC3S200A-4FTG256C的Datasheet PDF文件第92页  
Pinout Descriptions  
Footprint Migration Differences  
Unconnected Balls on XC3S50A  
Table 73: FT256 XC3S50A Footprint Migration  
Table 73 summarizes any footprint and functionality  
differences between the XC3S50A and the XC3S200A or  
XC3S400A FPGAs that might affect easy migration between  
these devices in the FT256 package. The XC3S200A and  
XC3S400A have identical pinouts. The XC3S50A pinout is  
compatible, but there are 52 balls that are different.  
Generally, designs easily migrate upward from the  
XC3S50A to either the XC3S200A or XC3S400A. If using  
differential I/O, see Table 74. If using the BPI configuration  
mode (parallel Flash), see Table 75.  
XC3S200A/  
XC3S400A  
Type  
FT256  
Ball  
XC3S50A  
Type  
Bank  
3
Migration  
Æ
K4  
K13  
L1  
N.C.  
I/O  
1
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
Æ
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
3
Æ
L2  
3
Æ
L3  
3
Æ
L4  
3
Æ
Table 73: FT256 XC3S50A Footprint Migration Difference  
L13  
L14  
L16  
M3  
1
Æ
XC3S200A/  
FT256  
Ball  
XC3S50A  
Type  
XC3S400A  
Type  
1
Æ
Bank  
0
Migration  
Æ
1
Æ
A7  
A12  
B12  
C7  
N.C.  
I/O  
3
Æ
0
N.C.  
INPUT  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
N.C.  
Æ
I/O  
M10  
M13  
M14  
M15  
M16  
N7  
2
Æ
0
Æ
I/O  
1
Æ
0
Æ
I/O  
1
Æ
D10  
E2  
0
Æ
I/O  
1
Æ
3
Æ
I/O  
1
Æ
E3  
3
Æ
I/O  
2
Æ
E7  
0
Æ
I/O  
N10  
N12  
P6  
2
Æ
E10  
E16  
F3  
0
Æ
I/O  
2
Æ
1
Æ
I/O  
2
Æ
3
Æ
I/O  
P13  
R7  
2
Æ
F8  
0
Æ
I/O  
2
Æ
F14  
F15  
F16  
G3  
1
Æ
I/O  
T7  
2
Æ
1
Æ
I/O  
DIFFERENCES  
Legend:  
52  
1
Æ
I/O  
3
Æ
I/O  
This pin can unconditionally migrate from the device  
on the left to the device on the right. Migration in the  
other direction is possible depending on how the pin is  
configured for the device on the right.  
Æ
G4  
3
Æ
I/O  
G5  
3
Æ
INPUT  
INPUT  
I/O  
G6  
3
Æ
G13  
G14  
G16  
H4  
1
Æ
1
Æ
I/O  
1
Æ
I/O  
3
Æ
I/O  
H5  
3
Æ
I/O  
H6  
3
Æ
I/O  
H13  
J4  
1
Æ
I/O  
3
Æ
I/O  
J6  
3
Æ
I/O  
J10  
J11  
1
Æ
INPUT  
INPUT  
1
Æ
88  
www.xilinx.com  
DS529-4 (v2.0) August 19, 2010  
 
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