Pinout Descriptions
User I/Os by Bank
Table 70, Table 71, and Table 72 indicate how the available
user-I/O pins are distributed between the four I/O banks on
the FT256 package. The AWAKE pin is counted as a
dual-purpose I/O.
The XC3S50A FPGA in the FT256 package has 51
unconnected balls, labeled with an “N.C.” type. These pins
are also indicated in Figure 20.
Table 70: User I/Os Per Bank on XC3S50A in the FT256 Package
All Possible I/O Pins by Type
Package
I/O Bank
Maximum I/O
Edge
I/O
21
12
5
INPUT
DUAL
VREF
CLK
8
Top
0
1
2
3
40
32
7
5
1
4
3
3
Right
8
Bottom
Left
40
2
21
0
6
6
32
15
53
6
3
8
TOTAL
144
20
26
15
30
.
Table 71: User I/Os Per Bank on XC3S200A and XC3S400A in the FT256 Package
All Possible I/O Pins by Type
Package
Edge
I/O Bank
Maximum I/O
I/O
27
1
INPUT
DUAL
1
VREF
CLK
8
Top
0
1
2
3
47
50
6
6
5
5
Right
30
21
0
8
Bottom
Left
48
11
30
69
2
6
8
50
7
5
8
TOTAL
195
21
52
21
32
Table 72: User I/Os Per Bank on XC3S700A and XC3S1400A in the FT256 Package
All Possible I/O Pins by Type
Package
Edge
I/O Bank
Maximum I/O
I/O
27
0
INPUT
DUAL
1
VREF
CLK
8
Top
0
1
2
3
41
40
1
0
0
1
2
4
4
Right
30
21
0
6
Bottom
Left
41
7
5
8
39
25
59
5
8
TOTAL
161
52
18
30
DS529-4 (v2.0) August 19, 2010
www.xilinx.com
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XILINX [ XILINX, INC ]
