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Spartan-3A FPGA Family:
Pinout Descriptions
DS529-4 (v2.0) August 19, 2010
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Product Specification
Introduction
This section describes how the various pins on a
Spartan®-3A FPGA connect within the supported
component packages, and provides device-specific thermal
characteristics. For general information on the pin functions
and the package characteristics, see the Packaging section
of UG331:
Spartan-3 Generation FPGA User Guide.
•
UG331: Spartan-3 Generation FPGA User Guide
Except for the thermal characteristics, all information for the
standard package applies equally to the Pb-free package.
Pin Types
Most pins on a Spartan-3A FPGA are general-purpose,
user-defined I/O pins. There are, however, up to 12 different
functional types of pins on Spartan-3A FPGA packages, as
outlined in
In the package footprint drawings that
follow, the individual pins are color-coded according to pin
type as in the table.
Spartan-3A FPGAs are available in both standard and
Pb-free, RoHS versions of each package, with the Pb-free
version adding a “G” to the middle of the package code.
Table 57:
Types of Pins on Spartan-3A FPGAs
Type / Color
Code
I/O
INPUT
Description
Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form
differential I/Os.
Unrestricted, general-purpose input-only pin. This pin does not have an output structure,
differential termination resistor, or PCI clamp diode.
Dual-purpose pin used in some configuration modes during the configuration process and
then usually available as a user I/O after configuration. If the pin is not used during
configuration, this pin behaves as an I/O-type pin. See
Spartan-3 Generation
Configuration User Guide
for additional information on these signals.
Pin Name(s) in Type
IO_#
IO_Lxxy_#
IP_#
IP_Lxxy_#
M[2:0]
PUDC_B
CCLK
MOSI/CSI_B
D[7:1]
D0/DIN
DOUT
CSO_B
RDWR_B
INIT_B
A[25:0]
VS[2:0]
LDC[2:0]
HDC
IP/VREF_#
IP_Lxxy_#/VREF_#
IO/VREF_#
IO_Lxxy_#/VREF_#
DUAL
VREF
Dual-purpose pin that is either a user-I/O pin or Input-only pin, or, along with all other
VREF pins in the same bank, provides a reference voltage input for certain I/O standards.
If used for a reference voltage within a bank, all VREF pins within the bank must be
connected.
CLK
Either a user-I/O pin or an input to a specific clock buffer driver. Most packages have 16 IO_Lxxy_#/GCLK[15:0],
global clock inputs that optionally clock the entire device. The exceptions are the TQ144 IO_Lxxy_#/LHCLK[7:0],
and the XC3S50A in the FT256 package). The RHCLK inputs optionally clock the right half IO_Lxxy_#/RHCLK[7:0]
of the device. The LHCLK inputs optionally clock the left half of the device. See the Using
Global Clock Resources chapter in
Spartan-3 Generation FPGA User Guide
for
additional information on these signals.
Dedicated configuration pin, two per device. Not available as a user-I/O pin. Every
package has two dedicated configuration pins. These pins are powered by VCCAUX. See
the
Spartan-3 Generation Configuration User Guide
for additional information on
the DONE and PROG_B signals.
DONE, PROG_B
CONFIG
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DS529-4 (v2.0) August 19, 2010
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