DC and Switching Characteristics
IEEE 1149.1/1532 JTAG Test Access Port Timing
TCCH
TCCL
TCK
(Input)
1/FTCK
TTCKTMS
TTMSTCK
TMS
(Input)
TTDITCK
TTCKTDI
TDI
(Input)
TTCKTDO
TDO
(Output)
DS099_06_020709
Figure 16: JTAG Waveforms
Table 56: Timing for the JTAG Test Access Port
All Speed
Grades
Symbol
Description
Min
Max
11.0
–
Units
ns
Clock-to-Output Times
TTCKTDO The time from the falling transition on the TCK pin to data appearing at the TDO pin
1.0
Setup Times
TTDITCK The time from the setup of data at the All devices and functions except those shown below
TDI pin to the rising transition at the
7.0
ns
Boundary scan commands (INTEST, EXTEST,
SAMPLE) on XC3S700A and XC3S1400A FPGAs
11.0
TCK pin
TTMSTCK The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin
7.0
–
–
ns
ns
Hold Times
TTCKTDI The time from the rising transition at
the TCK pin to the point when data is
last held at the TDI pin
All functions except those shown below
0
Configuration commands (CFG_IN, ISC_PROGRAM)
2.0
TTCKTMS The time from the rising transition at the TCK pin to the point when a logic level is last held at the
TMS pin
0
–
ns
Clock Timing
TCCH
TCCL
The High pulse width at the TCK pin All functions except ISC_DNA command
The Low pulse width at the TCK pin
5
5
–
–
ns
ns
TCCHDNA The High pulse width at the TCK pin During ISC_DNA command
TCCLDNA The Low pulse width at the TCK pin
10
10
0
10,000
10,000
33
ns
ns
FTCK
Frequency of the TCK signal
All operations on XC3S50A, XC3S200A, and
XC3S400A FPGAs and for BYPASS or HIGHZ
instructions on all FPGAs
MHz
All operations on XC3S700A and XC3S1400A FPGAs,
except for BYPASS or HIGHZ instructions
20
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
2. For details on JTAG see Chapter 9 “JTAG Configuration Mode and Boundary-Scan” in UG332 Spartan-3 Generation Configuration User
Guide.
DS529-3 (v2.0) August 19, 2010
www.xilinx.com
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XILINX [ XILINX, INC ]
