Spartan-3E FPGA Family: Pinout Descriptions
FG484: 484-ball Fine-pitch Ball Grid Array
The 484-ball fine-pitch ball grid array, FG484, supports the
XC3S1600E FPGA.
Table 153: FG484 Package Pinout (Cont’d)
XC3S1600E
Pin Name
FG484
Ball
Bank
Type
Table 153 lists all the FG484 package pins. They are sorted
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO_L12P_0
IO_L13N_0
A15
H14
G14
G13
F13
J13
H13
E12
F12
C12
B12
B11
C11
D11
E11
A9
I/O
I/O
IO_L13P_0
I/O
IO_L15N_0
I/O
An electronic version of this package pinout table and
footprint diagram is available for download from the Xilinx
website at:
IO_L15P_0
I/O
IO_L16N_0
I/O
IO_L16P_0
I/O
http://www.xilinx.com/support/documentation/data_sheets
/s3e_pin.zip
IO_L18N_0/GCLK5
IO_L18P_0/GCLK4
IO_L19N_0/GCLK7
IO_L19P_0/GCLK6
IO_L21N_0/GCLK11
IO_L21P_0/GCLK10
IO_L22N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
Pinout Table
Table 153: FG484 Package Pinout
XC3S1600E
Pin Name
FG484
Ball
Bank
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IO
IO
B6
I/O
I/O
IO_L22P_0
I/O
B13
C5
IO_L24N_0
I/O
IO
I/O
IO_L24P_0
A10
D10
C10
H8
I/O
IO
C14
E16
F9
I/O
IO_L25N_0/VREF_0
IO_L25P_0
VREF
I/O
IO
I/O
IO
I/O
IO_L27N_0
I/O
IO
F16
G8
I/O
IO_L27P_0
H9
I/O
IO
I/O
IO_L28N_0
C9
I/O
IO
H10
H15
J11
G12
C18
C19
A20
A21
A19
A18
C16
D16
A16
A17
B15
C15
G15
F15
D14
E14
A14
I/O
IO_L28P_0
B9
I/O
IO
I/O
IO_L29N_0
E9
I/O
IO
I/O
IO_L29P_0
D9
I/O
IO/VREF_0
IO_L01N_0
IO_L01P_0
IO_L03N_0/VREF_0
IO_L03P_0
IO_L04N_0
IO_L04P_0
IO_L06N_0
IO_L06P_0
IO_L07N_0
IO_L07P_0
IO_L09N_0/VREF_0
IO_L09P_0
IO_L10N_0
IO_L10P_0
IO_L11N_0
IO_L11P_0
IO_L12N_0/VREF_0
VREF
I/O
IO_L30N_0
B8
I/O
IO_L30P_0
A8
I/O
I/O
IO_L32N_0/VREF_0
IO_L32P_0
F7
VREF
I/O
VREF
I/O
F8
IO_L33N_0
A6
I/O
I/O
IO_L33P_0
A7
I/O
I/O
IO_L35N_0
A4
I/O
I/O
IO_L35P_0
A5
I/O
I/O
IO_L36N_0
E7
I/O
I/O
IO_L36P_0
D7
I/O
I/O
IO_L38N_0/VREF_0
IO_L38P_0
D6
VREF
I/O
VREF
I/O
D5
IO_L39N_0
B4
I/O
I/O
IO_L39P_0
B3
I/O
I/O
IO_L40N_0/HSWAP
IO_L40P_0
D4
DUAL
I/O
I/O
C4
I/O
IP
B19
INPUT
VREF
DS312 (v4.2) December 14, 2018
www.xilinx.com
Product Specification
217
XILINX [ XILINX, INC ]
