Spartan-3E FPGA Family: Pinout Descriptions
User I/Os by Bank
Table 152 indicates how the 304 available user-I/O pins are
distributed between the four I/O banks on the FG400
package.
Table 152: User I/Os Per Bank for the XC3S1200E and XC3S1600E in the FG400 Package
All Possible I/O Pins by Type
Package
I/O Bank
Maximum I/O
Edge
(2)
I/O
INPUT
DUAL
VREF(1)
CLK
Top
0
1
2
3
78
74
43
20
1
6
6
8
Right
35
12
21
24
0
0(2)
0(2)
8
Bottom
Left
78
30
18
6
74
48
12
6
TOTAL
304
156
62
46
24
16
Notes:
1. Some VREF and CLK pins are on INPUT pins.
2. The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Footprint Migration Differences
The XC3S1200E and XC3S1600E FPGAs have identical
footprints in the FG400 package. Designs can migrate
between the XC3S1200E and XC3S1600E FPGAs without
further consideration.
DS312 (v4.2) December 14, 2018
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