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XC3S100E-4VQG100CS1 参数 Datasheet PDF下载

XC3S100E-4VQG100CS1图片预览
型号: XC3S100E-4VQG100CS1
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 572MHz, 2160-Cell, CMOS, PQFP100,]
分类和应用: 时钟可编程逻辑
文件页数/大小: 227 页 / 6528 K
品牌: XILINX [ XILINX, INC ]
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Spartan-3E FPGA Family: Pinout Descriptions  
Footprint Migration Differences  
Table 146 summarizes any footprint and functionality  
differences between the XC3S250E, the XC3S500E, and  
the XC3S1200E FPGAs that may affect easy migration  
between devices in the FG256 package. There are 26 such  
balls. All other pins not listed in Table 146 unconditionally  
migrate between Spartan-3E devices available in the FT256  
package.  
and the XC3S1200E. The arrows indicate the direction for  
easy migration. A double-ended arrow () indicates that  
the two pins have identical functionality. A left-facing arrow  
() indicates that the pin on the device on the right  
unconditionally migrates to the pin on the device on the left.  
It may be possible to migrate the opposite direction  
depending on the I/O configuration. For example, an I/O pin  
(Type = I/O) can migrate to an input-only pin  
The XC3S250E is duplicated on both the left and right sides  
of the table to show migrations to and from the XC3S500E  
(Type = INPUT) if the I/O pin is configured as an input.  
Table 146: FT256 Footprint Migration Differences  
FT256  
Ball  
XC3S250E  
Type  
XC3S250E  
Migration XC3S1200E Type Migration  
Type  
Bank  
Migration  
XC3S500E Type  
B6  
B7  
0
0
0
0
1
1
1
3
3
3
3
3
3
1
1
3
2
1
3
2
1
1
2
2
2
2
INPUT  
N.C.  
  
INPUT  
I/O  
I/O  
26  
INPUT  
N.C.  
  
I/O  
B10  
C7  
INPUT  
N.C.  
  
INPUT  
I/O  
I/O  
INPUT  
N.C.  
  
  
  
  
  
  
I/O  
D16  
E13  
E16  
F3  
VREF(I/O)  
N.C.  
VREF(INPUT)  
I/O  
VREF(INPUT)  
VREF(I/O)  
N.C.  
I/O  
N.C.  
I/O  
I/O  
N.C.  
N.C.  
I/O  
I/O  
N.C.  
F4  
N.C.  
VREF  
I/O  
VREF  
INPUT  
VREF  
I/O  
N.C.  
F5  
I/O  
  
I/O  
L2  
N.C.  
VREF  
I/O  
  
  
  
  
  
  
N.C.  
L3  
N.C.  
N.C.  
L4  
N.C.  
I/O  
I/O  
N.C.  
L12  
L13  
M4  
M7  
M14  
N2  
N.C.  
I/O  
I/O  
N.C.  
N.C.  
I/O  
I/O  
N.C.  
N.C.  
I/O  
I/O  
N.C.  
INPUT  
I/O  
  
  
  
INPUT  
I/O  
I/O  
INPUT  
I/O  
INPUT  
VREF(INPUT)  
I/O  
VREF(I/O)  
N.C.  
VREF(I/O)  
I/O  
VREF(I/O)  
N.C.  
N7  
  
  
  
  
  
  
N14  
N15  
P7  
N.C.  
I/O  
I/O  
N.C.  
N.C.  
VREF  
I/O  
VREF  
I/O  
N.C.  
N.C.  
N.C.  
P10  
R10  
T12  
N.C.  
I/O  
I/O  
N.C.  
N.C.  
VREF  
INPUT  
VREF  
I/O  
N.C.  
INPUT  
  
19  
INPUT  
DIFFERENCES  
7
Legend:  
This pin is identical on the device on the left and the right.  
  
This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be  
possible depending on how the pin is configured for the device on the right.  
This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be  
possible depending on how the pin is configured for the device on the left.  
DS312 (v4.2) December 14, 2018  
www.xilinx.com  
Product Specification  
195  
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