R
Functional Description
levels (see Table 2 of Module 3). At this time, all I/O drivers
are in a high-impedance state. VCCO Bank 2, VCCINT, and
loaded design reverses the polarity of their respective SR
inputs.
V
CCAUX serve as inputs to the internal Power-On Reset cir-
The Global Three State (GTS) net is released during
Start-Up, marking the end of configuration and the begin-
ning of design operation in the User mode. After the GTS
net is released, all user I/Os go active while all unused I/Os
are weakly pulled down (PULLDOWN). The designer can
control how the unused I/Os are terminated after GTS is
released by setting the Bitstream Generator (BitGen) option
UnusedPin to PULLUP, PULLDOWN, or FLOAT.
cuit (POR).
A Low level applied to the HSWAP input enables pull-up
resistors on User I/Os from power-on throughout configura-
tion. A High level on HSWAP disables the pull-up resistors,
allowing the I/Os to float. HSWAP contains a weak pull-up
and defaults to High if left floating. As soon as power is
applied, the FPGA begins initializing its configuration mem-
ory. At the same time, the FPGA internally asserts the Glo-
bal Set-Reset (GSR), which asynchronously resets all IOB
storage elements to a default Low state.
One clock cycle later (default), the Global Write Enable
(GWE) net is released allowing the RAM and registers to
change states. Once in User mode, any pull-up resistors
enabled by HSWAP revert to the user settings and HSWAP
is available as a general-purpose I/O. For more information
on PULLUP and PULLDOWN, see Pull-Up and Pull-Down
Resistors.
Upon the completion of initialization and the beginning of
configuration, INIT_B goes High, sampling the M0, M1, and
M2 inputs to determine the configuration mode. At this point
in time, the configuration data is loaded into the FPGA. The
I/O drivers remain in a high-impedance state (with or with-
out pull-up resistors, as determined by the HSWAP input)
throughout configuration.
JTAG Boundary-Scan Capability
All Spartan-3E IOBs support boundary-scan testing com-
patible with IEEE 1149.1/1532 standards. See JTAG Mode,
page 86 for more information on programming via JTAG.
At the end of configuration, the GSR net is released, placing
the IOB registers in a Low state by default, unless the
12
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
