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XC3S1600E-4FGG320C 参数 Datasheet PDF下载

XC3S1600E-4FGG320C图片预览
型号: XC3S1600E-4FGG320C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- 3E FPGA系列 [Spartan-3E FPGA Family]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 193 页 / 1733 K
品牌: XILINX [ XILINX, INC ]
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Functional Description  
and additional multiplexers and carry logic simplify wide  
logic and arithmetic functions. Most general-purpose logic  
in a design is automatically mapped to the slice resources in  
the CLBs. Each CLB is identical, and the Spartan-3E family  
CLB structure is identical to that for the Spartan-3 family.  
Configurable Logic Block (CLB) and  
Slice Resources  
CLB Overview  
The Configurable Logic Blocks (CLBs) constitute the main  
logic resource for implementing synchronous as well as  
combinatorial circuits. Each CLB contains four slices, and  
each slice contains two Look-Up Tables (LUTs) to imple-  
ment logic and two dedicated storage elements that can be  
used as flip-flops or latches. The LUTs can be used as a  
16x1 memory (RAM16) or as a 16-bit shift register (SRL16),  
CLB Array  
The CLBs are arranged in a regular array of rows and col-  
umns as shown in Figure 11.  
Each density varies by the number of rows and columns of  
CLBs (see Table 6).  
X0Y3 X1Y3  
X0Y2 X1Y2  
X2Y3 X3Y3  
X2Y2 X3Y2  
X0Y1 X1Y1  
X0Y0 X1Y0  
X2Y1 X3Y1  
X2Y0 X3Y0  
Spartan-3E  
FPGA  
IOBs  
Slice  
CLB  
DS312-2_31_021205  
Figure 11: CLB Locations  
Table 6: Spartan-3E CLB Resources  
CLB  
Rows  
CLB  
Columns  
CLB  
LUTs /  
Flip-Flops  
Equivalent  
Logic Cells  
RAM16 /  
SRL16  
Distributed  
RAM Bits  
Device  
Total(1)  
Slices  
960  
XC3S100E  
XC3S250E  
XC3S500E  
XC3S1200E  
XC3S1600E  
22  
34  
46  
60  
76  
16  
26  
34  
46  
58  
240  
1920  
2160  
5508  
960  
2448  
4656  
8672  
14752  
15360  
39168  
74496  
138752  
236032  
612  
2448  
4656  
8672  
14752  
4896  
1164  
2168  
3688  
9312  
10476  
19512  
33192  
17344  
29504  
Notes:  
1. The number of CLBs is less than the multiple of the rows and columns because the block RAM/multiplier blocks and the DCMs are  
embedded in the array (see Module 1, Figure 1).  
LUTs support both logic and memory (including both  
Slices  
RAM16 and SRL16 shift registers) while half support logic  
Each CLB comprises four interconnected slices, as shown  
only, and the two types alternate throughout the array col-  
in Figure 13. These slices are grouped in pairs. Each pair is  
umns. The SLICEL reduces the size of the CLB and lowers  
organized as a column with an independent carry chain.  
the cost of the device, and can also provide a performance  
The left pair supports both logic and memory functions and  
advantage over the SLICEM.  
its slices are called SLICEM. The right pair supports logic  
only and its slices are called SLICEL. Therefore half the  
DS312-2 (v1.1) March 21, 2005  
www.xilinx.com  
13  
Advance Product Specification