R
Functional Description
Table 3: Single-Ended IOSTANDARD Bank Compatibility
VCCO Supply/Compatibility
Input Requirements
Board
VREF for
Termination
Single-Ended
IOSTANDARD
Inputs
N/R
N/R
N/R
N/R
N/R
N/R(1)
N/R
N/R
N/R
0.9
1.2 V
1.5 V
1.8 V
2.5 V
3.0 V
3.3 V
Voltage (VTT)
Input/
Output
LVTTL
-
-
-
-
-
N/R
Input/
Output
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
-
-
-
-
-
-
-
-
-
-
-
N/R
N/R
N/R
N/R
N/R
N/R
N/R
N/R
0.9
Input/
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input/
Output
Input
Input
Input
-
Input/
Output
Input
Input/
Output
Input
Input
Input/
Output
-
-
-
-
-
-
Input/
Output
PCI66_3
-
Input/
Output
PCIX
Input/
Output
HSTL_I_18
HSTL_III_18
SSTL18_I
-
-
-
-
-
-
-
-
Input
Input
Input
Input
Input
Input
Input
Input/
Output
1.1
1.8
Input/
Output
0.9
0.9
Input/
Output
SSTL2_I
-
1.25
1.25
Notes:
1. N/R - Not required for input operation.
8
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DS312-2 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
