R
Pinout Descriptions
FG484: 484-ball Fine-pitch Ball Grid Array
The 484-ball fine-pitch ball grid array, FG484, supports the
XC3S1600E FPGA.
Table 31: FG484 Package Pinout
XC3S1600E
FG484
Ball
Table 31 lists all the FG484 package pins. They are sorted
by bank number and then by pin name. Pairs of pins that
form a differential I/O pair appear together in the table. The
table also shows the pin number for each pin and the pin
type, as defined earlier.
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Pin Name
Type
I/O
IO_L10P_0
F15
D14
E14
A14
A15
H14
G14
G13
F13
J13
H13
E12
F12
C12
B12
B11
C11
D11
E11
A9
IO_L11N_0
I/O
IO_L11P_0
I/O
An electronic version of this package pinout table and foot-
print diagram is available for download from the Xilinx web-
IO_L12N_0/VREF_0
IO_L12P_0
VREF
I/O
site at http://www.xilinx.com/bvdocs/publications/s3e_pin.zip
.
IO_L13N_0
I/O
Pinout Table
IO_L13P_0
I/O
Table 31: FG484 Package Pinout
IO_L15N_0
I/O
XC3S1600E
Pin Name
FG484
Ball
IO_L15P_0
I/O
Bank
0
Type
I/O
IO_L16N_0
I/O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
B6
IO_L16P_0
I/O
0
B13
C5
I/O
IO_L18N_0/GCLK5
IO_L18P_0/GCLK4
IO_L19N_0/GCLK7
IO_L19P_0/GCLK6
IO_L21N_0/GCLK11
IO_L21P_0/GCLK10
IO_L22N_0
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
I/O
0
I/O
0
C14
E16
F9
I/O
0
I/O
0
I/O
0
F16
G8
I/O
0
I/O
0
H10
H15
J11
G12
C18
C19
A20
A21
A19
A18
C16
D16
A16
A17
B15
C15
G15
I/O
IO_L22P_0
I/O
0
I/O
IO_L24N_0
I/O
0
I/O
IO_L24P_0
A10
D10
C10
H8
I/O
0
IO/VREF_0
VREF
I/O
IO_L25N_0/VREF_0
IO_L25P_0
VREF
I/O
0
IO_L01N_0
0
IO_L01P_0
I/O
IO_L27N_0
I/O
0
IO_L03N_0/VREF_0
IO_L03P_0
VREF
I/O
IO_L27P_0
H9
I/O
0
IO_L28N_0
C9
I/O
0
IO_L04N_0
I/O
IO_L28P_0
B9
I/O
0
IO_L04P_0
I/O
IO_L29N_0
E9
I/O
0
IO_L06N_0
I/O
IO_L29P_0
D9
I/O
0
IO_L06P_0
I/O
IO_L30N_0
B8
I/O
0
IO_L07N_0
I/O
IO_L30P_0
A8
I/O
0
IO_L07P_0
I/O
IO_L32N_0/VREF_0
IO_L32P_0
F7
VREF
I/O
0
IO_L09N_0/VREF_0
IO_L09P_0
VREF
I/O
F8
0
IO_L33N_0
A6
I/O
0
IO_L10N_0
I/O
62
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
