R
Pinout Descriptions
FG400 Footprint
Bank 0
1
2
3
4
5
6
7
8
10
9
Left Half of Package
(top view)
I/O
L17N_0
GCLK11
I/O
L17P_0
GCLK10
I/O
L30N_0
INPUT
L28N_0
INPUT
L28P_0
I/O
L24N_0
I/O
L24P_0
GND
I/O
I/O
A
B
C
D
E
F
I/O
L21N_0
VREF_0
I/O
L03P_3
I/O
L30P_0
I/O
L26N_0
I/O
L26P_0
I/O
L21P_0
VCCO_0
VCCO_0
I/O
TDI
GND
I/O
I/O: Unrestricted,
156
general-purpose user I/O
I/O
L29N_0
VREF_0
I/O
L03N_3
I/O
L31P_0
I/O
L27P_0
INPUT
L22N_0
I/O
L20N_0
PROG_B
GND
INPUT: User I/O or
reference resistor input for
bank
62
I/O
L31N_0
HSWAP
I/O
L04P_3
I/O
L01N_3
I/O
L01P_3
I/O
L29P_0
I/O
L27N_0
INPUT
L22P_0
I/O
L20P_0
VCCO_0
GND
DUAL: Configuration pin,
then possible user I/O
46
24
16
2
I/O
L02N_3
VREF_3
I/O
L15N_0
GCLK7
I/O
L04N_3
I/O
L02P_3
INPUT
L25N_0
INPUT
L25P_0
I/O
L18P_0
VCCO_3
INPUT
INPUT
I/O
VREF: User I/O or input
voltage reference for bank
I/O
L23N_0
VREF_0
I/O
L06N_3
I/O
L06P_3
I/O
L05N_3
I/O
L05P_3
I/O
L23P_0
I/O
L18N_0
VCCO_0
GND
GCLK: User I/O, input, or
clock buffer input
INPUT
L16N_0
GCLK9
I/O
L07P_3
I/O
L07N_3
I/O
L08N_3
INPUT
L19P_0
INPUT
L19N_0
INPUT
INPUT
GND
INPUT
I/O
G
H
J
CONFIG: Dedicated
configuration pins
I/O
L09N_3
VREF_3
INPUT
L16P_0
GCLK8
I/O
L09P_3
I/O
L08P_3
I/O
L10P_3
I/O
L10N_3
VCCO_3
GND
VCCINT
GND
VCCINT
GND
JTAG: Dedicated JTAG
port pins
4
I/O
L12N_3
I/O
L12P_3
I/O
L11P_3
I/O
L11N_3
I/O
L13N_3
VCCAUX
INPUT
VCCINT
GND
GND: Ground
I/O
L14N_3
LHCLK1
I/O
L14P_3
LHCLK0
I/O
L15P_3
LHCLK2
42
24
16
8
INPUT
VREF_3
I/O
L13P_3
VCCAUX
GND
VCCINT
GND
K
L
VCCO: Output voltage
supply for bank
I/O
L15N_3
LHCLK3
IRDY2
I/O
L16N_3
LHCLK5
I/O
L17N_3
LHCLK7
VCCO_3
VCCO_3
GND
INPUT
INPUT
VCCINT
GND
VCCINT: Internal core
supply voltage (+1.2V)
I/O
L16P_3
LHCLK4
TRDY2
I/O
L17P_3
LHCLK6
I/O
L19N_3
I/O
L19P_3
I/O
L20P_3
I/O
L18N_3
I/O
L18P_3
INPUT
VCCINT
VCCAUX
GND
M
N
P
R
T
VCCAUX: Auxiliary supply
voltage (+2.5V)
I/O
L20N_3
VREF_3
I/O
L21P_3
I/O
L21N_3
I/O
L23P_3
I/O
L23N_3
I/O
L22P_3
INPUT
VCCINT
I/O
VCCINT
I/O
L16N_2
D3
GCLK15
N.C.: Not connected
0
I/O
L24P_3
I/O
L25P_3
INPUT
VREF_3
I/O
L22N_3
VCCO_3
GND
INPUT
I/O
I/O
L09N_2
VREF_2
I/O
L24N_3
I/O
L26P_3
I/O
L27P_3
I/O
L27N_3
I/O
L25N_3
INPUT
L11N_2
L16P_2
D4
GND
I/O
GCLK14
I/O
L28N_3
VREF_3
INPUT
L14N_2
VREF_2
I/O
L26N_3
I/O
L29N_3
I/O
L06P_2
I/O
L06N_2
I/O
L09P_2
INPUT
L11P_2
INPUT
L14P_2
INPUT
I/O
L03P_2
DOUT
BUSY
I/O
L01P_2
CSO_B
I/O
L28P_3
I/O
L29P_3
INPUT
L05P_2
I/O
L07N_2
I/O
L12N_2
VCCO_3
VCCO_2
VCCAUX
U
V
W
Y
I/O
I/O
I/O
L01N_2
INIT_B
I/O
L30N_3
I/O
L30P_3
INPUT
L05N_2
I/O
L07P_2
I/O
L10N_2
I/O
L12P_2
L03N_2
MOSI
L18P_2
D2
GND
CSI_B
GCLK2
I/O
I/O
INPUT
L02P_2
I/O
L04P_2
INPUT
L08P_2
I/O
L10P_2
L15P_2
D7
L15N_2
D6
VCCO_2
INPUT
GND
INPUT
GND
I/O
GCLK12
GCLK13
INPUT
L02N_2
I/O
VREF_2
I/O
L04N_2
INPUT
L08N_2
I/O
L13N_2
I/O
L13P_2
I/O
GND
Bank 2
DS312-4_08_031105
Figure 9: FG400 Package Footprint (top view)
60
www.xilinx.com
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
