072
R
Spartan-3E FPGA Family:
Pinout Descriptions
0
0
DS312-4 (v1.1) March 21, 2005
Advance Product Specification
Introduction
Pin Types
This section describes the various pins on a Spartan™-3E
FPGA and how they connect within the supported compo-
nent packages.
A majority of the pins on a Spartan-3E FPGA are gen-
eral-purpose, user-defined I/O pins. There are, however, up
to 11 different functional types of pins on Spartan-3E pack-
ages, as outlined in Table 1. In the package footprint draw-
ings that follow, the individual pins are color-coded
according to pin type as in the table.
Table 1: Types of Pins on Spartan-3E FPGAs
Type /
Color Code
Description
Pin Name(s) in Type
I/O
Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to IO
form differential I/Os.
IO_Lxxy_#
INPUT
DUAL
Unrestricted, general-purpose input-only pin. This pin does not have an output IP
structure.
IP_Lxxy_#
Dual-purpose pin used in some configuration modes during the configuration
M[2:0]
process and then usually available as a user I/O after configuration. If the pin is HSWAP
not used during configuration, this pin behaves as an I/O-type pin. Some of the CCLK
dual-purpose pins are also global or edge clock inputs (GCLK).
MOSI/CSI_B
D[7:1]
D0/DIN
CSO_B
RDWR_B
BUSY/DOUT
INIT_B
A[23:20]
A19/VS2
A18/VS1
A17/VS0
A[16:0]
LDC[2:0]
HDC
VREF
Dual-purpose pin that is either a user-I/O pin or, along with all other VREF pins IP/VREF_#
in the same bank, provides a reference voltage input for certain I/O standards. IP_Lxx_#/VREF_#
If used for a reference voltage within a bank, all VREF pins within the bank must
be connected.
GCLK
Either a user-I/O pin or an input to a specific clock buffer driver. Every package GCLK[15:0],
LHCLK
RHCLK
has 16 global clock inputs that optionally clock the entire device. The RHCLK
inputs optionally clock the right-hand side of the device. The LHCLK inputs
optionally clock the left-hand side of the device. Some of the clock pins are
shared with the dual-purpose configuration pins and are considered DUAL-type.
LHCLK[7:0],
RHCLK[7:0]
CONFIG
Dedicated configuration pin. Not available as a user-I/O pin. Every package has DONE, PROG_B
two dedicated configuration pins. These pins are powered by VCCAUX.
© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.
All other trademarks are the property of their respective owners.
DS312-4 (v1.1) March 21, 2005
www.xilinx.com
1
Advance Product Specification
XILINX [ XILINX, INC ]
