R
DC and Switching Characteristics
PROG_B
(Input)
INIT_B
(Open-Drain)
TSMCSCC
TSMCCCS
CS_B
(Input)
TSMCCW
TSMWCC
RDWR_B
(Input)
TCCH
TCCL
CCLK
(Input)
1/FCCPAR
Byte n
TSMDCC
TSMCCD
D0 - D7
(Inputs)
Byte 0
Byte 1
Byte n+1
TSMCKBY
TSMCKBY
High-Z
High-Z
BUSY
(Output)
BUSY
DS312-3_02_020805
Notes:
1. It is possible to abort configuration by pulling CS_B Low in a given CCLK cycle, then switching RDWR_B Low or High in any subsequent
cycle for which CS_B remains Low. The RDWR_B pin asynchronously controls the driver impedance of the D0 - D7 bus. When RDWR_B
switches High, be careful to avoid contention on the D0 - D7 bus.
Figure 5: Waveforms for Slave Parallel Configuration
Table 18: Timing for the Slave Parallel Configuration Mode
All Speed Grades
Symbol
Description
Min
Max
Units
Clock-to-Output Times
TSMCKBY
The time from the rising transition on the CCLK pin to a signal transition at the
BUSY pin
-
12.0
ns
Setup Times
TSMDCC
The time from the setup of data at the D0-D7 pins to the rising transition at the
CCLK pin
10.0
10.0
10.0
-
-
-
ns
ns
ns
TSMCSCC
The time from the setup of a logic level at the CS_B pin to the rising transition
at the CCLK pin
(2)
TSMCCW
The time from the setup of a logic level at the RDWR_B pin to the rising
transition at the CCLK pin
DS312-3 (v1.0) March 1, 2005
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Advance Product Specification
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