R
DC and Switching Characteristics
PROG_B
(Input)
INIT_B
(Open-Drain)
TCCL
TCCH
CCLK
(Input/Output)
TDCC
1/FCCSER
TCCD
DIN
(Input)
Bit n+1
TCCO
Bit n
Bit 0
Bit 1
DOUT
(Output)
Bit n-63
Bit n-64
DS099-3_04_071604
Figure 4: Waveforms for Master and Slave Serial Configuration
Table 17: Timing for the Master and Slave Serial Configuration Modes
All Speed Grades
Slave/
Symbol
Description
Master
Min
Max
Units
Clock-to-Output Times
TCCO
The time from the falling transition on the CCLK pin to data
appearing at the DOUT pin
Both
Both
Both
Slave
1.5
12.0
ns
Setup Times
TDCC
The time from the setup of data at the DIN pin to the rising transition
at the CCLK pin
10.0
0
-
-
ns
ns
Hold Times
TCCD
The time from the rising transition at the CCLK pin to the point when
data is last held at the DIN pin
Clock Timing
TCCH
The High pulse width at the CCLK input pin
The Low pulse width at the CCLK input pin
5.0
-
-
ns
ns
TCCL
5.0
FCCSER
Frequency of the clock signal at
the CCLK input pin
No bitstream compression
With bitstream compression
-
-
66(2)
20
MHz
MHz
-
∆FCCSER Variation from the CCLK output frequency set using the ConfigRate
Master
–50%
+50%
BitGen option
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 4.
2. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
14
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DS312-3 (v1.0) March 1, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
