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XC3S1600E-4FGG320C 参数 Datasheet PDF下载

XC3S1600E-4FGG320C图片预览
型号: XC3S1600E-4FGG320C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- 3E FPGA系列 [Spartan-3E FPGA Family]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 193 页 / 1733 K
品牌: XILINX [ XILINX, INC ]
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R
DC and Switching Characteristics  
Table 7: Recommended Operating Conditions for User I/Os Using Single-Ended Standards  
V
CCO for Drivers(2)  
VREF  
VIL  
VIH  
Min (V)  
VREF + 0.1  
VREF + 0.1  
0.8  
IOSTANDARD  
Attribute  
Min (V) Nom (V) Max (V) Min (V)  
Nom (V)  
Max (V)  
Max (V)  
HSTL_I_18  
HSTL_III_18  
LVCMOS12(4)  
LVCMOS15(4)  
LVCMOS18(4)  
LVCMOS25(4,5)  
LVCMOS33(4)  
LVTTL  
1.7  
1.7  
1.1  
1.4  
1.65  
2.3  
3.0  
3.0  
-
1.8  
1.8  
1.2  
1.5  
1.8  
2.5  
3.3  
3.3  
3.0  
3.0  
TBD  
1.80  
2.5  
1.9  
1.9  
1.3  
1.6  
1.95  
2.7  
3.45  
3.45  
-
0.8  
0.9  
1.1  
V
REF - 0.1  
VREF - 0.1  
0.38  
-
1.1  
-
-
-
-
-
-
-
0.38  
0.8  
-
-
-
0.38  
0.8  
-
-
-
0.7  
1.7  
-
-
-
0.8  
2.0  
-
-
-
0.8  
2.0  
PCI33_3(7)  
PCI66_3(7)  
PCIX(7)  
-
-
-
0.9  
1.5  
-
-
-
-
-
-
-
-
0.9  
1.5  
-
-
TBD  
TBD  
SSTL18_I  
1.70  
2.3  
1.90  
2.7  
0.833  
1.15  
0.900  
1.25  
0.969  
1.35  
V
REF - 0.125 VREF + 0.125  
SSTL2_I  
VREF - 0.15 VREF + 0.15  
Notes:  
1. Descriptions of the symbols used in this table are as follows:  
V
V
V
V
-- the supply voltage for output drivers  
-- the reference voltage for setting the input switching threshold  
-- the input voltage that indicates a Low logic level  
-- the input voltage that indicates a High logic level  
CCO  
REF  
IL  
IH  
2. The V  
rails supply only output drivers, not input circuits.  
CCO  
3. For device operation, the maximum signal voltage (V max) may be as high as V max. See Table 1.  
IH  
IN  
4. There is approximately 100 mV of hysteresis on inputs using any LVCMOS standard.  
5. All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) use the LVCMOS25 standard and draw power from the V  
rail (2.5V).  
CCAUX  
The Dual-Purpose configuration pins use the LVCMOS25 standard before the User mode. When using these pins as part of a standard 2.5V  
configuration interface, apply 2.5V to the V lines of Banks 0, 1, and 2 at power-on as well as throughout configuration.  
CCO  
6. The Global Clock Inputs (GCLK0-GCLK15, RHCLK0-RHCLK7, and LHCLK0-LHCLK7) are Dual-Purpose pins to which any signal standard  
may be assigned.  
7. For more information, see "Virtex-II Pro and Spartan-3 3.3V PCI Reference Design" (XAPP653).  
DS312-3 (v1.0) March 1, 2005  
www.xilinx.com  
5
Advance Product Specification