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XC3S1600E-4FGG320C 参数 Datasheet PDF下载

XC3S1600E-4FGG320C图片预览
型号: XC3S1600E-4FGG320C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- 3E FPGA系列 [Spartan-3E FPGA Family]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 193 页 / 1733 K
品牌: XILINX [ XILINX, INC ]
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018
R
Spartan-3E FPGA Family:
DC and Switching
Characteristics
0
DS312-3 (v1.0) March 1, 2005
0
Advance Product Specification
DC Electrical Characteristics
In this section, specifications may be designated as
Advance, Preliminary, or Production. These terms are
defined as follows:
Advance:
Initial estimates are based on simulation, early
characterization, and/or extrapolation from the characteris-
tics of other families. Values are subject to change. Use as
estimates, not for production.
Preliminary:
Based on characterization. Further changes
are not expected.
Production:
These specifications are approved once the
silicon has been characterized over numerous production
lots. Parameter values are considered stable with no future
changes expected.
All parameter limits are representative of worst-case supply
voltage and junction temperature conditions.
The following
applies unless otherwise noted: The parameter values
published in this module apply to all Spartan™-3E
devices. AC and DC characteristics are specified using
the same numbers for both commercial and industrial
grades.
If a particular Spartan-3E FPGA differs in functional
behavior or electrical characteristic from this data
sheet, those differences are described in a separate
errata document. The errata documents for Spartan-3E
FPGAs are living documents and are available
.
Table 1:
Absolute Maximum Ratings
Symbol
V
CCINT
V
CCAUX
V
CCO
V
REF
V
IN(2)
Description
Internal supply voltage
Auxiliary supply voltage
Output driver supply voltage
Input reference voltage
Voltage applied to all User I/O pins and
Dual-Purpose pins
Voltage applied to all Dedicated pins
V
ESD
Electrostatic Discharge Voltage
Human body model
Charged device model
Machine model
T
J
T
STG
Notes:
1.
2.
3.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only;
functional operation of the device at these or any other conditions beyond those listed under the Recommended Operating Conditions is not
implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time adversely affects device reliability.
As a rule, the V
IN
limits apply to both the DC and AC components of signals. Simple application solutions are available that show how to
handle overshoot/undershoot as well as achieve PCI compliance. Refer to the following application notes: "Virtex™-II Pro and Spartan-3
3.3V PCI Reference Design" (XAPP653) and "Using 3.3V I/O Guidelines in a Virtex-II Pro Design" (XAPP659).
Each of the User I/O and Dual-Purpose pins is associated with one of the four banks’ V
CCO
rails. Meeting the V
IN
max limit ensures that the
internal diode junctions that exist between these pins and their associated V
CCO
rails do not turn on.
specifies the V
CCO
range used
to determine the max limit. When V
CCO
is at its maximum recommended operating level (3.45V), V
IN
max is 3.95V. The maximum voltage
that avoids oxide stress is V
INX
= 4.05V. As long as the V
IN
max specification is met, oxide stress is not possible.
All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) draw power from the V
CCAUX
rail (2.5V). Meeting the V
IN
max limit ensures
that the internal diode junctions that exist between each of these pins and the V
CCAUX
rail do not turn on.
specifies the V
CCAUX
range
used to determine the max limit. When V
CCAUX
is at its maximum recommended operating level (2.625V), V
IN
max < 3.125V. As long as the
V
IN
max specification is met, oxide stress is not possible.
For soldering guidelines, see "Device Packaging and Thermal Characteristics" at
Also see
"Implementation and Solder Reflow Guidelines for Pb-Free Packages" at
Conditions
Min
–0.5
–0.5
–0.5
–0.5
Max
1.32
3.00
3.75
V
CCO
+ 0.5
(3)
V
CCO
+ 0.5
(3)
V
CCAUX
+ 0.5
(4)
+2000
+500
+200
125
150
Units
V
V
V
V
V
V
V
V
V
°C
°C
Driver in a high-impedance state
–0.5
–0.5
–2000
–500
–200
-
–65
Junction temperature
Storage temperature
4.
5.
© 2005 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc.
All other trademarks are the property of their respective owners.
DS312-3 (v1.0) March 1, 2005
Advance Product Specification
1