R
DC and Switching Characteristics
Table 8: DC Characteristics of User I/Os Using Single-Ended Standards (Continued)
Test Conditions Logic Level Characteristics
IOL
IOH
VOL
VOH
IOSTANDARD Attribute
SSTL2_I
(mA)
(mA)
Max (V)
Min (V)
8.1
–8.1
VTT - 0.61
VTT + 0.61
Notes:
1. The numbers in this table are based on the conditions set forth in Table 4 and Table 7.
2. Descriptions of the symbols used in this table are as follows:
I
I
-- the output current condition under which V is tested
OL
OL
-- the output current condition under which V is tested
OH
OH
V
-- the output voltage that indicates a Low logic level
OL
V
-- the output voltage that indicates a High logic level
-- the input voltage that indicates a Low logic level
-- the input voltage that indicates a High logic level
-- the supply voltage for output drivers
-- the reference voltage for setting the input switching threshold
OH
V
V
V
V
V
IL
IH
CCO
REF
-- the voltage applied to a resistor termination
TT
3. For the LVCMOS and LVTTL standards: the same V and V limits apply for both the Fast and Slow slew attributes.
OL
OH
4. All Dedicated output pins (DONE and TDO) as well as Dual-Purpose totem-pole output pins (CCLK, D0-D7, BUSY/DOUT, CSO_B, MOSI,
HDC, LDC0-LDC2, and A0-A23) exhibit the characteristics of LVCMOS25 with Slow slew rate; all have 8 mA drive except CCLK, which has
12 mA drive.
5. Tested according to the relevant PCI specifications. For more information, see "Virtex-II Pro and Spartan-3 3.3V PCI Reference Design"
(XAPP653).
DS312-3 (v1.0) March 1, 2005
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7
Advance Product Specification
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