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XC3S1600E-4FGG320C 参数 Datasheet PDF下载

XC3S1600E-4FGG320C图片预览
型号: XC3S1600E-4FGG320C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- 3E FPGA系列 [Spartan-3E FPGA Family]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 193 页 / 1733 K
品牌: XILINX [ XILINX, INC ]
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Functional Description  
Table 57: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued)  
Pins/Function  
Affected  
Values  
(default)  
Option Name  
Description  
GWE_cycle  
All flip-flops,  
LUT RAMs,  
and SRL16  
shift registers,  
Block RAM,  
Configuration  
Startup  
1, 2, 3, 4, Selects the Configuration Startup phase that asserts the internal write-enable signal to  
5, 6  
all flip-flops, LUT RAMs and shift registers (SRL16). It also enables block RAM read  
and write operations. See Start-Up, page 91.  
Done  
Waits for the DONE pin input to go High before asserting the internal write-enable  
signal to all flip-flops, LUT RAMs and shift registers (SRL16). Block RAM read and  
write operations are enabled at this time.  
Keep  
Retains the current GWE_cycle setting for partial reconfiguration applications.  
GTS_cycle  
All I/O pins,  
1, 2, 3, 4, Selects the Configuration Startup phase that releases the internal three-state control,  
Configuration  
5, 6  
holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive, if so  
configured, after this point. See Start-Up, page 91.  
Done  
Waits for the DONE pin input to go High before releasing the internal three-state  
control, holding all I/O buffers in high-impedance (Hi-Z). Output buffers actively drive,  
if so configured, after this point.  
Keep  
Retains the current GTS_cycle setting for partial reconfiguration applications.  
The FPGA does not wait for selected DCMs to lock before completing configuration.  
LCK_cycle  
DCMs,  
Configuration  
Startup  
NoWait  
0, 1, 2, 3, If one or more DCMs in the design have the STARTUP_WAIT attribute set to TRUE,  
4, 5, 6  
the FPGA waits for such DCMs to acquire their respective input clock and assert their  
LOCKED output. This setting selects the Configuration Startup phase where the FPGA  
waits for the DCMs to lock.  
DonePin  
DONE pin  
DONE pin  
Pullup  
Internally connects a pull-up resistor between DONE pin and VCCAUX. An external  
330 pull-up resistor to VCCAUX is still recommended.  
Pullnone No internal pull-up resistor on DONE pin. An external 330 pull-up resistor to  
VCCAUX is required.  
DriveDone  
No  
When configuration completes, the DONE pin stops driving Low and relies on an  
external 330 pull-up resistor to VCCAUX for a valid logic High.  
Yes  
When configuration completes, the DONE pin actively drives High. When using this  
option, an external pull-up resistor is no longer required. Only one device in an FPGA  
daisy-chain should use this setting.  
DonePipe  
ProgPin  
DONE pin  
No  
The input path from DONE pin input back to the Startup sequencer is not pipelined.  
Yes  
This option adds a pipeline register stage between the DONE pin input and the Startup  
sequencer. Used for high-speed daisy-chain configurations when DONE cannot rise in  
a single CCLK cycle. Releases GWE and GTS signals on the first rising edge of  
StartupClk after the DONE pin input goes High.  
PROG_B pin  
Pullup  
Internally connects a pull-up resistor or between PROG_B pin and VCCAUX. An  
external 4.7 kpull-up resistor to VCCAUX is still recommended.  
Pullnone No internal pull-up resistor on PROG_B pin. An external 4.7 kpull-up resistor to  
VCCAUX is required.  
TckPin  
TdiPin  
JTAG TCK pin  
JTAG TDI pin  
Pullup  
Internally connects a pull-up resistor between JTAG TCK pin and VCCAUX.  
Pulldown Internally connects a pull-down resistor between JTAG TCK pin and GND.  
Pullnone No internal pull-up resistor on JTAG TCK pin.  
Pullup  
Internally connects a pull-up resistor between JTAG TDI pin and VCCAUX.  
Pulldown Internally connects a pull-down resistor between JTAG TDI pin and GND.  
Pullnone No internal pull-up resistor on JTAG TDI pin.  
DS312-2 (v1.1) March 21, 2005  
www.xilinx.com  
93  
Advance Product Specification