R
Functional Description
The relative timing of configuration events is programmed
via the Bitstream Generator (BitGen) options in the Xilinx
development software. For example, the GTS and GWE
events can be programmed to wait for all the DONE pins to
High on all the devices in a multiple-FPGA daisy-chain, forc-
ing the FPGAs to start synchronously. Similarly, the start-up
sequence can be paused at any stage, waiting for selected
DCMs to lock to their respective input clock signals. See
also Stabilizing DCM Clocks Before User Mode, page 48.
Along with the configuration data, it is possible to read back
the contents of all registers, distributed RAM, and block
RAM resources. This capability is used for real-time debug-
ging.
To synchronously control when registers values are cap-
tured for readback, using the CAPTURE_SPARTAN3 library
primitive, which applies for both Spartan-3 and Spartan-3E
FPGA families.
Bitstream Generator (BitGen) Options
The start-up sequence can by synchronized to a clock
within
the
FPGA
application
using
the
Various Spartan-3E FPGA functions are controlled by spe-
cific bits in the configuration bitstream image. These values
are specified when creating the bitstream image with the
Bitstream Generator (BitGen) software.
STARTUP_SPARTAN3E library primitive and by setting the
StartupClk bitstream generator option. The FPGA applica-
tion can optionally assert the Global Set/Reset (GSR) and
Global Three-State signal (GTS) signals via the
STARTUP_SPARTAN3E primitive.
Table 57 provides a list of all BitGen options for Spartan-3E
FPGAs.
Readback
Using Slave Parallel mode, configuration data from the
FPGA can be read back. Readback is supported only in the
Slave Parallel and JTAG modes.
Table 57: Spartan-3E FPGA Bitstream Generator (BitGen) Options
Pins/Function
Affected
Values
(default)
Option Name
Description
ConfigRate
CCLK,
Configuration
3, 6,
12, 25
Sets the approximate frequency, in MHz, of the internal oscillator using for Master
Serial, SPI, and BPI configuration modes. The internal oscillator powers up at its lowest
frequency and the new setting is loaded as part of the configuration bitstream. The
software default value is 6 (~6 MHz).
StartupClk
Configuration,
Startup
Cclk
Default. The CCLK signal (internally or externally generated) controls the startup
sequence when the FPGA transitions from configuration mode to the user mode. See
Start-Up, page 91.
UserClk
A clock signal from within the FPGA application controls the startup sequence when
the FPGA transitions from configuration mode to the user mode. See Start-Up,
page 91. The FPGA application supplies the user clock on the CLK pin on the
STARTUP_SPARTAN3E primitive.
Jtag
The JTAG TCK input controls the startup sequence when the FPGA transitions from
configuration mode to the user mode. See Start-Up, page 91.
UnusedPin
Unused I/O
Pins
Pulldown Default. All unused I/O pins have a pull-down resistor to GND.
Pullup
All unused I/O pins have a pull-up resistor to the VCCO_# supply for its associated I/O
bank.
Pullnone All unused I/O pins are left floating (Hi-Z, high-impedance, three-state). Use external
pull-up or pull-down resistors or logic to apply a valid signal level.
DONE_cycle
DONE pin,
Configuration
Startup
1, 2, 3, 4, Selects the Configuration Startup phase that activates the FPGA’s DONE pin. See
5, 6
Start-Up, page 91.
92
www.xilinx.com
DS312-2 (v1.1) March 21, 2005
Advance Product Specification
XILINX [ XILINX, INC ]
