— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Table 5: Minimum Power On Current Required for Virtex-II Devices
Device (mA)
XC2V40, XC2V80,
XC2V250, XC2V500 XC2V1000 XC2V1500 XC2V2000
XC2V3000 XC2V4000
XC2V6000 XC2V8000
ICCINTMIN
ICCAUXMIN
ICCOMIN
200
100
50
250
100
50
350
100
100
400
100
100
500
100
100
650
100
100
800
100
100
1100
100
100
Notes:
1. Values specified for power on current parameters are Commercial Grade. For Industrial Grade values, multiply Commercial Grade
values by 1.25.
2. ICCOMIN values listed here apply to the entire device (all banks).
General Power Supply Requirements
Proper decoupling of all FPGA power supplies is sessential.
Consult Xilinx Application Note XAPP623 for detailed infor-
mation on power distribution system design.
tion are provided in Xilinx Answer Record 13756, available
at www.support.xilinx.com.
V
V
can share a power plane with 3.3V V
does not have excessive noise. Using simultaneously
, but only if
CCO
CCAUX
V
V
powers critical resources in the FPGA. Thus,
is especially susceptible to power supply noise.
CCAUX
CCAUX
CCO
switching output (SSO) limits are essential for keeping
power supply noise to a minimum. Refer to XAPP689, “Man-
aging Ground Bounce in Large FPGAs,” to determine the
number of simultaneously switching outputs allowed per
bank at the package level.
Changes in V
voltage outside of 200 mV peak to peak
CCAUX
should take place at a rate no faster than 10 mV per milli-
second. Techniques to help reduce jitter and period distor-
DC Input and Output Levels
Values for V and V are recommended input voltages.
sen to ensure that all standards meet their specifications.
IL
IH
Values for I
and I
are guaranteed over the recom-
The selected standards are tested at minimum V
with
OL
OH
CCO
mended operating conditions at the V
and V
test
the respective V and V
voltage levels shown. Other
OL
OH
OL
OH
points. Only selected standards are tested. These are cho-
standards are sample tested.
Table 6: DC Input and Output Levels
V
V
V
V
I
I
OH
Input/Output
Standard
LVTTL(1)
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
PCI33_3
PCI66_3
PCI–X
IL
IH
OL
OH
OL
V, Min
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
– 0.5
V, Max
V, Min
2.0
V, Max
3.6
V, Max
0.4
V, Min
mA
24
mA
– 24
– 24
– 24
– 16
– 16
Note 2
Note 2
Note 2
n/a
0.8
0.8
0.7
2.4
2.0
3.6
0.4
V
CCO – 0.4
24
1.7
2.7
0.4
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
90% VCCO
90% VCCO
Note 2
24
35% VCCO
35% VCCO
30% VCCO
30% VCCO
Note 2
65% VCCO
65% VCCO
50% VCCO
50% VCCO
Note 2
1.95
0.4
16
1.7
0.4
16
VCCO + 0.5
VCCO + 0.5
Note 2
10% VCCO
10% VCCO
Note 2
0.6
Note 2
Note 2
Note 2
36
GTLP
V
REF – 0.1
REF – 0.05
VREF – 0.1
VREF + 0.1
VCCO + 0.5
VCCO + 0.5
VCCO + 0.5
VCCO + 0.5
VCCO + 0.5
VCCO + 0.5
n/a
GTL
V
VREF + 0.05
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
0.4
n/a
40
n/a
HSTL I
0.4
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
8
– 8
HSTL II
V
REF – 0.1
REF – 0.1
0.4
16
– 16
– 8
HSTL III
V
0.4
24
HSTL IV
VREF – 0.1
0.4
48
– 8
DS031-3 (v4.0) April 7, 2014
Product Specification
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