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R
Virtex-II Platform FPGAs: DC and Switching Characteristics
Table 12: Register-to-Register Performance (Continued)
Device Used & Speed
Register-to-Register
Performance
Description
Grade
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
292
239
114
114
110
88
8-bit Adder
16-bit Adder
64-bit Adder
64-bit Counter
64-bit Accumulator
Multiplier 18x18 (with Block RAM inputs)
Multiplier 18x18 (with Register inputs)
Memory
105
Block RAM
278
277
270
253
257
259
250
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Single-Port 4096 x 4 bits
Single-Port 2048 x 9 bits
Single-Port 1024 x 18 bits
Single-Port 512 x 36 bits
Dual-Port A:4096 x 4 bits & B:1024 x 18 bits
Dual-Port A:1024 x 18 bits & B:1024 x 18 bits
Dual-Port A:2048 x 9 bits & B: 512 x 36 bits
Distributed RAM
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
387
335
266
409
311
294
MHz
MHz
MHz
MHz
MHz
MHz
Single-Port 32 x 8-bit
Single-Port 64 x 8-bit
Single-Port 128 x 8-bit
Dual-Port 16 x 8
Dual-Port 32 x 8
Dual-Port 64 x 8
Shift Registers
N/A
N/A
MHz
MHz
128-bit SRL
256-bit SRL
FIFOs (Async. in Block RAM)
1024 x 18-bit Read
279
172
MHz
MHz
1024 x 18-bit Write
FIFOs (Sync. in SRL)
128 x 8-bit
N/A
N/A
MHz
MHz
128 x 16-bit
DS031-3 (v4.0) April 7, 2014
Product Specification
www.xilinx.com
Module 3 of 4
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