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XC2S400E-6FG456C 参数 Datasheet PDF下载

XC2S400E-6FG456C图片预览
型号: XC2S400E-6FG456C
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- IIE FPGA [Spartan-IIE FPGA]
分类和应用:
文件页数/大小: 108 页 / 5063 K
品牌: XILINX [ XILINX, INC ]
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Spartan-IIE FPGA Family:  
Pinout Tables  
DS077-4 (2.3) June 18, 2008  
0
Product Specification  
Introduction  
Pin Types  
This section describes how the various pins on a  
Most pins on a Spartan-IIE FPGA are general-purpose,  
user-defined I/O pins. There are, however, different  
functional types of pins on Spartan-IIE FPGA packages, as  
outlined below.  
Spartan®-IIE FPGA connect within the supported  
component packages, and provides device-specific thermal  
characteristics. Spartan-IIE FPGAs are available in both  
standard and Pb-free, RoHS versions of each package, with  
the Pb-free version adding a “G” to the middle of the  
package code. Except for the thermal characteristics, all  
information for the standard package applies equally to the  
Pb-free package.  
Pin Definitions  
Dedicated  
Pad Name  
Pin  
Direction  
Description  
GCK0, GCK1, GCK2,  
GCK3  
No  
Input  
Clock input pins that connect to Global Clock buffers or DLL  
inputs. These pins become user inputs when not needed for  
clocks.  
DLL  
No  
Input  
Input  
Clock input pins that connect to DLL input or feedback clocks.  
Differential clock input (N input of pair) when paired with adjacent  
GCK input. Becomes a user I/O when not needed for clocks.  
M0, M1, M2  
CCLK  
Yes  
Yes  
Mode pins used to specify the configuration mode.  
Input or Output The configuration Clock I/O pin. It is an input for Slave Parallel  
and Slave Serial modes, and output in Master Serial mode. After  
configuration, it is an input only with Don’t Care logic levels.  
PROGRAM  
DONE  
Yes  
Yes  
Input  
Initiates a configuration sequence when asserted Low.  
Bidirectional  
Indicates that configuration loading is complete, and that the  
start-up sequence is in progress. The output may be open drain.  
INIT  
No  
Bidirectional  
(Open-drain)  
When Low, indicates that the configuration memory is being  
cleared. Goes High to indicate the end of initialization. Goes back  
Low to indicate a CRC error. This pin becomes a user I/O after  
configuration.  
DOUT/BUSY  
No  
Output  
In Slave Parallel mode, BUSY controls the rate at which  
configuration data can be loaded. It is not needed below 50 MHz.  
This pin becomes a user I/O after configuration unless the Slave  
Parallel port is retained.  
In serial modes, DOUT provides configuration data to  
downstream devices in a daisy-chain. This pin becomes a user  
I/O after configuration.  
© 2003-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, the Brand Window, and other designated brands included herein are trademarks of Xilinx, Inc. All other  
trademarks are the property of their respective owners.  
DS077-4 (2.3) June 18, 2008  
www.xilinx.com  
53  
Product Specification  
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