R
Spartan-IIE FPGA Family: DC and Switching Characteristics
DIN
T
T
T
CCD
CCL
DCC
CCLK
T
CCH
T
CCO
DOUT
(Output)
DS001_16_032300
.
All Devices
Symbol
Description
Min
Max
Units
TDCC
TCCD
/
DIN setup/hold
5 / 0
-
ns
TCCO
TCCH
TCCL
FCC
DOUT
-
5
5
-
12
-
ns
ns
CCLK
High time
Low time
-
ns
Maximum frequency
66
MHz
Figure 24: Slave Serial Mode Timing
CCLK
(Output)
T
CKDS
T
DSCK
Serial Data In
T
CCO
Serial DOUT
(Output)
DS001_17_110101
Units
ns
.
All Devices
Symbol
Description
DIN setup/hold
Min
Max
TDSCK
/
5 / 0
-
TCKDS
TCCO
FCC
CCLK DOUT
Frequency tolerance with respect to
nominal
-
12
ns
-
–30%
+45%
Figure 25: Master Serial Mode Timing
DS077-3 (v2.3) June 18, 2008
www.xilinx.com
49
Product Specification
XILINX [ XILINX, INC ]
