R
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
X-Ref Target - Figure 1
IOBs
CLB
DCM
IOBs
DCM
CLBs
IOBs
DCM
Block RAM / DSP48A Slice
IOBs
Notes:
IOBs
DSP48A Slice
Block RAM
DS705_01_061908
1
.
The XA3SD1800A and XA3SD3400A have two DCMs on both the left and right sides, as well as the two DCMs at the top and
bottom of the devices. The two DCMs on the left and right of the chips are in the middle of the outer block RAM/DSP48A
columns of the 4 or 5 columns in the selected device, as shown in the diagram above.
2. A detailed diagram of the DSP48A can be found in
XtremeDSP DSP48A for Spartan-3A DSP FPGAs User Guide.
Figure 1:
XA Spartan-3A DSP Family Architecture
Configuration
XA Spartan-3A DSP FPGAs are programmed by loading
configuration data into robust, reprogrammable, static
CMOS configuration latches (CCLs) that collectively control
all functional elements and routing resources. The FPGA’s
configuration data is stored externally in a PROM or some
other non-volatile medium, either on or off the board.
After applying power, the configuration data is written to the
FPGA using any of five different modes:
•
•
•
•
Serial Peripheral Interface (SPI) from an industry-
standard SPI serial Flash
Byte Peripheral Interface (BPI) Up from an industry-
standard x8 or x8/x16 parallel NOR Flash
Slave Serial, typically downloaded from a processor
Slave Parallel, typically downloaded from a processor
•
Boundary-Scan (JTAG), typically downloaded from a
processor or system tester
Additionally, each XA Spartan-3A DSP FPGA contains a
unique, factory-programmed Device DNA identifier useful
for tracking purposes, anti-cloning designs, or IP protection.
DS705 (v1.1) January 20, 2009
Product Specification
3
XILINX [ XILINX, INC ]
