54
R
XA Spartan-3A DSP Automotive
FPGA Family Data Sheet
Product Specification
DS705 (v1.1) January 20, 2009
Summary
The Xilinx Automotive (XA) Spartan®-3A DSP family of FPGAs
solves the design challenges in most high-volume, cost-sensitive,
high-performance DSP automotive applications. The two-member
family offers densities ranging from 1.8 to 3.4 million system gates,
as shown in
♦
Integrated adder for complex multiply or multiply-add operation
♦
Integrated 18-bit pre-adder
♦
Optional cascaded Multiply or MAC
Dual-range V
CCAUX
supply simplifies 3.3V-only design
Suspend and Hibernate modes reduce system power
Multi-voltage, multi-standard SelectIO™ interface pins
♦
Up to 519 I/O pins or 227 differential signal pairs
♦
LVCMOS, LVTTL, HSTL, and SSTL single-ended I/O
♦
3.3V, 2.5V, 1.8V, 1.5V, and 1.2V signaling
♦
Selectable output drive, up to 24 mA per pin
♦
QUIETIO standard reduces I/O switching noise
♦
Full 3.3V
±
10% compatibility and hot-swap compliance
♦
622+ Mb/s data transfer rate per differential I/O
♦
LVDS, RSDS, mini-LVDS, HSTL/SSTL differential I/O with
♦
Enhanced Double Data Rate (DDR) support
♦
DDR/DDR2 SDRAM support up to 266 Mb/s
♦
Fully compliant 32-bit, 33 MHz PCI® technology support
Abundant, flexible logic resources
♦
Densities up to 53,712 logic cells, including optional shift register
♦
Efficient wide multiplexers, wide logic
♦
Fast look-ahead carry logic
♦
IEEE 1149.1/1532 JTAG programming/debug port
Hierarchical SelectRAM™ memory architecture
♦
Up to 2,268 Kbits of fast block RAM with byte write enables for
♦
♦
•
processor applications
Up to 373 Kbits of efficient distributed RAM
Registered outputs on the block RAM with operation of at least
280 MHz in the standard -4 speed grade
integrated differential termination resistors
•
•
•
Introduction
XA devices are available in both extended-temperature Q-Grade
(–40°C to +125°C T
J
) and I-Grade (–40°C to +100°C T
J
) and are
qualified to the industry recognized AEC-Q100 standard.
The XA Spartan-3A DSP family builds on the success of the earlier
XA Spartan-3E and XA Spartan-3 FPGA families by adding
hardened DSP MACs with pre-adders, significantly increasing the
throughput and performance of this low-cost family. These XA
Spartan-3A DSP family enhancements, combined with proven
90 nm process technology, deliver more functionality and
bandwidth per dollar than ever before, setting the new standard in
the programmable logic industry.
Because of their exceptionally low cost, XA Spartan-3A DSP
FPGAs are ideally suited to a wide range of automotive electronics
applications, including infotainment, driver information, and driver
assistance modules.
The XA Spartan-3A DSP family is a superior alternative to mask
programmed ASICs. FPGAs avoid the high initial mask set costs
and lengthy development cycles, while also permitting design
upgrades in the field with no hardware replacement necessary
because of its inherent programmability, an impossibility with
conventional ASICs and ASSPs with their inflexible architecture.
•
•
•
•
Features
•
•
Very low cost, high-performance DSP solution for high-
volume, cost-conscious applications
250 MHz DSP48A slices using XtremeDSP™ solution
♦
Dedicated 18-bit by 18-bit multiplier
♦
Available pipeline stages for enhanced performance of at least
♦
250 MHz in the standard -4 speed grade
48-bit accumulator for multiply-accumulate (MAC) operation
•
•
•
Eight Digital Clock Managers (DCMs)
♦
Clock skew elimination (delay locked loop)
♦
Frequency synthesis, multiplication, division
♦
High-resolution phase shifting
♦
Wide frequency range (5 MHz to over 320 MHz)
Eight low-skew global clock networks, eight additional clocks
per half device, plus abundant low-skew routing
Configuration interface to industry-standard PROMs
♦
Low-cost, space-saving SPI serial Flash PROM
♦
x8 or x8/x16 parallel NOR Flash PROM
♦
Unique Device DNA identifier for design authentication
Complete Xilinx
and
software support plus
and
embedded processor cores
BGA packaging, Pb-free only
♦
Common footprints support easy density migration
Table 1:
Summary of XA Spartan-3A DSP FPGA Attributes
Device
XA3SD1800A
XA3SD3400A
CLB Array (One CLB = Four Slices) Distributed
System Equivalent
RAM
Total
Gates Logic Cells Rows Columns Total
Bits
(
1
)
CLBs
Slices
1800K
3400K
37,440
53,712
88
104
48
58
4,160
5,968
16,640
23,872
260K
373K
Block
RAM
Bits
(
1
)
1512K
2268K
DSP48As
84
126
Maximum
DCMs Maximum Differential
User I/O
I/O Pairs
8
8
519
469
227
213
Notes:
1. By convention, one Kb is equivalent to 1,024 bits.
© 2008–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. PCI, PCIe, and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS705 (v1.1) January 20, 2009
Product Specification
1
XILINX [ XILINX, INC ]
