R
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
For information regarding reliability qualification, refer to
RPT103,
Xilinx Spartan-3A Family Automotive Qualification
Report
and RPT070,
Spartan-3A Commercial Qualification
Report.
Contact your local Xilinx representative for more
details on these reports.
Refer to
Spartan-3A DSP FPGA Family Data Sheet
for a full product description, AC and DC specifications, and
package pinout descriptions. Any values shown specifically
in this XA Spartan-3A DSP Automotive FPGA Family data
sheet override those shown in DS610.
Key Feature Differences from Commercial XC Devices
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AEC-Q100 device qualification and full production part
approval process (PPAP) documentation support
available in both extended temperature I- and
Q-Grades
Guaranteed to meet full electrical specifications over
the T
J
= –40°C to +125°C temperature range
(Q-Grade)
XA Spartan-3A DSP devices are available in the
-4 speed grade only
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PCI-66 and PCI-X are not supported in the XA
Spartan-3A DSP FPGA product line
Platform Flash is not supported within the XA family
XA Spartan-3A DSP devices are available in Pb-free
packaging only
MultiBoot is not supported in XA versions of this
product.
The XA Spartan-3A DSP device must be power cycled
prior to reconfiguration.
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Architectural Overview
The XA Spartan-3A DSP family architecture consists of five
fundamental programmable functional elements:
•
XtremeDSP DSP48A Slice
provides an 18-bit x 18-bit
multiplier, 18-bit pre-adder, 48-bit post-
adder/accumulator, and cascade capabilities for
various DSP applications.
Configurable Logic Blocks (CLBs)
contain flexible
Look-Up Tables (LUTs) that implement logic plus
storage elements used as flip-flops or latches. CLBs
perform a wide variety of logical functions as well as
store data.
Input/Output Blocks (IOBs)
control the flow of data
between the I/O pins and the internal logic of the
device. IOBs support bidirectional data flow plus
3-state operation. Supports a variety of signal
standards, including several high-performance
differential standards. Double Data-Rate (DDR)
registers are included.
Block RAM
provides data storage in the form of
18-Kbit dual-port blocks.
Digital Clock Manager (DCM) Blocks
provide self-
calibrating, fully digital solutions for distributing,
delaying, multiplying, dividing, and phase-shifting clock
signals.
These elements are organized as shown in
A dual
ring of staggered IOBs surrounds a regular array of CLBs.
The XA3SD1800A has four columns of DSP48A slices, and
the XA3SD3400A has five columns of DSP48A slices. Each
DSP48A has an associated block RAM. The DCMs are
positioned in the center with two at the top and two at the
bottom of the device and in the two outer columns of the 4 or
5 columns of block RAM and DSP48As.
The XA Spartan-3A DSP family features a rich network of
routing that interconnect all five functional elements,
transmitting signals among them. Each functional element
has an associated switch matrix that permits multiple
connections to the routing.
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DS705 (v1.1) January 20, 2009
Product Specification
2
XILINX [ XILINX, INC ]
