R
Platform Flash XL High-Density Configuration and Storage Device
Status Register
The Status Register provides information on the current or
previous program or erase operations. A Read Status
Register command is issued to read the contents of the
Status Register, refer to "Read Status Register Command,"
page 14 for more details. To output the contents, the Status
Register is latched and updated on the falling edge of the
Chip Enable or Output Enable signals and can be read until
The various bits convey information about the status and
any errors of the operation. Bits SR7, SR6, SR2 and SR0
give information on the status of the device and are set and
reset by the device. Bits SR5, SR4, SR3 and SR1 give
information on errors and are set by the device but must be
reset by issuing a Clear Status Register command or a
hardware reset.
Chip Enable or Output Enable returns to V .
IH
If an error bit is set to ‘1’, the Status Register should be
reset before issuing another command.
The Status Register can only be read using single
asynchronous or synchronous reads. Bus Read operations
from any address within the bank always read the Status
Register during program and erase operations if no Read
Array command is issued.
The bits in the Status Register are summarized in Table 11.
Table 11: Status Register Bits
Logic
Bit
Name
Type
Definition
Level(1)
'1'
Ready
SR7
P/E.C. Status
Status
'0'
Busy
'1'
Erase suspended
SR6
SR5
SR4
SR3
SR2
SR1
Erase Suspend Status
Status
Error
Error
Error
Status
Error
'0'
Erase In progress or completed
Erase/blank check error
Erase/blank check success
Program error
'1'
Erase/Blank Check
Status
'0'
'1'
Program Status
VPP Status
'0'
Program success
'1'
VPP invalid, abort
'0'
VPP OK
'1'
Program suspended
Program Suspend
Status
'0'
Program In progress or completed
Program/erase on protected block, abort
No operation to protected block
'1'
Block Protection Status
'0'
SR7 = ‘1’
SR7 = ‘0’
SR7 = ‘1’
SR7 = ‘0’
SR7 = ‘1’
SR7 = ‘0’
SR7 = ‘1’
SR7 = ‘0’
Not allowed
'1'
'0'
'1'
'0'
Program or erase operation in a bank other
than the addressed bank
Bank Write Status
Status
Status
No program or erase operation in the device
Program or erase operation in addressed
bank
SR0
Not allowed
The device is NOT ready for the next Buffer
loading or is going to exit the BEFP mode
Multiple Word Program
Status (BufferEnhanced
Factory Program mode)
The device has exited the BEFP mode
The device is ready for the next Buffer
loading
Notes:
1. Logic level '1' is High, '0' is Low.
the Program/Erase Controller is active or inactive in any
bank. When this bit is Low (set to ‘0’), the Program/Erase
Program/Erase Controller Status Bit (SR7)
The Program/Erase Controller Status bit indicates whether
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
21
XILINX [ XILINX, INC ]
