R
Platform Flash XL High-Density Configuration and Storage Device
Configuration Register
The Configuration Register is used to configure the type of bus access that the memory performs. Refer to "Read Modes,"
page 34 for details on read operations.
The Configuration Register is set through the Command Interface using the Set Configuration Register command. After a
reset or power-up, the device is configured for Synchronous Read (CR15 = 0). The Configuration Register bits (Table 12,
page 26) specify the selection of the burst length, burst type, burst X latency, and read operation. Refer to Figure 9, page 28
and Figure 10, page 30 for examples of synchronous burst configurations.
Table 12: Configuration Register Bits
Bits
CR15
CR14
Description
Read mode
Reserved
Value
0
Description
Synchronous Read (default)
1
Asynchronous Read
0
010
011
100
101
110
111
2 clock latency(1)
3 clock latency
4 clock latency
CR13–CR11
Clock Latency
Wait Polarity
5 clock latency
6 clock latency
7 clock latency (default)
Other configurations reserved
0
1
READY_WAIT with Wait function (CR4 = 0) is active Low
CR10
CR9
CR8
CR7
READY_WAIT with Wait function (CR4 = 0) is active High (default)
0
Data held for 1 clock cycle (default)
Data output
configuration
1
Data held for 2 clock cycles(1)
0
Wait active during wait state
Wait Configuration
Burst Type
1
Wait active 1 clock cycle before wait state (default)
0
Reserved
1
Sequential (default)
0
Falling clock edge
CR6
CR5
CR4
Valid Clock Edge
Reserved
1
Rising clock edge (default)
0
–
0
READY_WAIT signal has the Wait function
Device_ready
1
READY_WAIT signal has the Ready function (default)
0
Wrap
CR3(2)
Wrap burst
1
No wrap (default)
4 words
001
010
011
111
8 words
CR2–CR0(2)
Burst Length
16 words
Continuous (default)
Notes:
1. The combination X-Latency = 2, Data held for two clock cycles and Wait active one data cycle before the WAIT state is not supported.
2. CR3 (wrap/no wrap) bit has no effect when CR2-CR0 (burst length) bits are set to continuous burst mode. Platform Flash XL wraps to the first
memory address after the device outputs the data from the last memory address.
DS617 (v3.0.1) January 07, 2010
www.xilinx.com
Product Specification
24
XILINX [ XILINX, INC ]
