R
Platform Flash XL High-Density Configuration and Storage Device
X-Ref Target - Figure 1
Platform Flash XL
READY_WAIT
Clock up to 50 MHz
(1)
FPGA Design
(.bit) File
Wide (16-bit) Datapath
Up to 800 Mb/s
SelectMAP (x16)
Port
Configuration
Synchronization
Handshake
FPGA
DS617_01_102709
Notes:
1.
System considerations can lower the configuration clock frequency below the maximum clock frequency for the device. To determine the
maximum configuration clock frequency, check the minimum clock period (T
KHKH
) for the chosen I/O voltage range (V
DDQ
), the clock High-
to-output valid time (T
KHQV
), and the FPGA SelectMAP setup time.
Figure 1:
Platform Flash XL Delivers Reliable, High-Performance FPGA Configuration
Platform Flash XL support is integrated with the Xilinx
design and debug tool suite.The iMPACT application,
included with the ISE software, supports indirect, in-system
programming of Platform Flash XL via the IEEE Standard
1149.1 (JTAG) port on the FPGA for prototype programming
(Figure
3).
X-Ref Target - Figure 2
Platform Flash XL
Code
User Data
Design (.bit)
File, Rev. 1
Design (.bit)
File, Rev. 0
Control
Address
FPGA
User Design
Data/Commands
DS617_02_081209
Figure 2:
Standard NOR Flash Interface for User
Access to Memory
X-Ref Target - Figure 3
Single Cable Connector for
Direct FPGA Configuration/Debug and
Indirect Platform Flash XL
Programming
IEEE 1149.1
(JTAG) Port
Xilinx JTAG
Cable Connector
FPGA
For Programming
Platform Flash XL
Platform Flash XL
Standard NOR
Flash Interface
FPGA Design
(.bit) File
Control
Address
Data/Commands
BPI Flash
Configuration Port
Indirect,
In-System
Programming
Engine
For Programming
Platform Flash XL
DS617_03_081209
Figure 3:
Indirect Programming Solution for Platform Flash XL
DS617 (v3.0.1) January 07, 2010
Product Specification
2
XILINX [ XILINX, INC ]
