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Functional Description
VARIABLE Phase Shift Mode
In VARIABLE phase shift mode, the FPGA application
dynamically adjusts the fine phase shift value using three
inputs to the PS unit (PSEN, PSCLK, and PSINCDEC), as
defined in Table 36 and shown in Figure 40.
Table 36: Signals for Variable Phase Mode
Signal
Direction
Input
Description
(1)
PSEN
Enables the Phase Shift unit for variable phase adjustment.
(1)
PSCLK
Input
Input
Clock to synchronize phase shift adjustment.
(1)
PSINCDEC
PSDONE
When High, increments the current phase shift value. When Low, decrements the
current phase shift value. This signal is synchronized to the PSCLK signal.
Output
Goes High to indicate that the present phase adjustment is complete and PS unit is
ready for next phase adjustment request. This signal is synchronized to the PSCLK
signal.
Notes:
1. This input supports either a true or inverted polarity.
The FPGA application uses the three PS inputs on the
Phase Shift unit to dynamically and incrementally increase
or decrease the phase shift amount on all nine DCM clock
outputs.
the PS unit subtracts one DCM_ DELAY_STEP of phase
shift from all nine DCM outputs.
Because each DCM_DELAY_STEP has a minimum and
maximum value, the actual phase shift delay for the present
phase increment/decrement value (VALUE) falls within the
minimum and maximum values according to Equation 4 and
Equation 5.
To adjust the current phase shift value, the PSEN enable
signal must be High to enable the PS unit. Coincidently,
PSINCDEC must be High to increment the current phase
shift amount or Low to decrement the current amount. All
VARIABLE phase shift operations are controlled by the
PSCLK input, which can be the CLKIN signal or any other
clock signal.
TPS(Max) = VALUE • DCM_DELAY_STEP_MAX
TPS(Min) = VALUE • DCM_DELAY_STEP_MIN
Eq. 4
Eq. 5
Design Note
The maximum variable phase shift steps, MAX_STEPS, is
described in Equation 6 or Equation 7, for a given CLKIN
The VARIABLE phase shift feature operates differently from
the Spartan-3 DCM but the DCM design primitive is com-
mon to both Spartan-3 and Spartan-3E design entry. Vari-
able phase shift in Spartan-3E FPGAs behaves as
described herein. However, the DCM design primitive and
simulation model does not match this behavior. Starting
with ISE 8.1i, Service Pack 3, using the VARIABLE attribute
generates an error message. The following Answer Record
describes how to re-enable the VARIABLE phase shift fea-
ture.
input period, T
, in nanoseconds. To convert this to a
CLKIN
phase shift range measured in time and not steps, use
MAX_STEPS derived in Equation 6 and Equation 7 for
VALUE in Equation 4 and Equation 5.
If CLKIN < 60 MHz:
MAX_STEPS = [INTEGER(10 • (TCLKIN – 3))]
Eq. 6
If CLKIN > 60 MHz:
http://www.xilinx.com/support/answers/23004.htm
MAX_STEPS = [INTEGER(15 • (TCLKIN – 3))]
Eq. 7
DCM_DELAY_STEP
The phase adjustment might require as many as 100 CLKIN
cycles plus 3 PSCLK cycles to take effect, at which point the
DCM’s PSDONE output goes High for one PSCLK cycle.
This pulse indicates that the PS unit completed the previous
adjustment and is now ready for the next request.
DCM_DELAY_STEP is the finest delay resolution available
in the PS unit. Its value is provided at the bottom of
Table 105 in Module 3. For each enabled PSCLK cycle that
PSINCDEC is High, the PS unit adds one DCM_
DELAY_STEP of phase shift to all nine DCM outputs. Simi-
larly, for each enabled PSCLK cycle that PSINCDEC is Low,
Asserting the Reset (RST) input returns the phase shift to
zero.
DS312-2 (v3.8) August 26, 2009
www.xilinx.com
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Product Specification
XILINX [ XILINX, INC ]
