R
Functional Description
By contrast, the clock switch matrixes on the top and bottom
edges receive signals from any of the five following sources:
two GCLK pins, two DCM outputs, or one Double-Line inter-
connect.
The four BUFGMUX elements on the top edge are paired
together and share inputs from the eight global clock inputs
along the top edge. Each BUFGMUX pair connects to four
of the eight global clock inputs, as shown in Figure 45. This
optionally allows differential inputs to the global clock inputs
without wasting a BUFGMUX element.
Table 41 indicates permissible connections between clock
inputs and BUFGMUX elements. The I0-input provides the
best input path to a clock buffer. The I1-input provides the
secondary input for the clock multiplexer function.
Table 41: Connections from Clock Inputs to BUFGMUX Elements and Associated Quadrant Clock
Quadrant
Clock
Line
Left-Half BUFGMUX
Top or Bottom BUFGMUX
Right-Half BUFGMUX
(1)
(2)
(2)
(2)
Location
I0 Input I1 Input Location
I0 Input
I1 Input Location
I0 Input I1 Input
GCLK7or GCLK6or
H
G
F
X0Y9
X0Y8
X0Y7
X0Y6
X0Y5
X0Y4
X0Y3
X0Y2
LHCLK7 LHCLK6
LHCLK6 LHCLK7
LHCLK5 LHCLK4
LHCLK4 LHCLK5
LHCLK3 LHCLK2
LHCLK2 LHCLK3
LHCLK1 LHCLK0
LHCLK0 LHCLK1
X1Y10
X1Y11
X2Y10
X2Y11
X1Y0
X3Y9
X3Y8
X3Y7
X3Y6
X3Y5
X3Y4
X3Y3
X3Y2
RHCLK3 RHCLK2
RHCLK2 RHCLK3
RHCLK1 RHCLK0
RHCLK0 RHCLK1
RHCLK7 RHCLK6
RHCLK6 RHCLK7
RHCLK5 RHCLK4
RHCLK4 RHCLK5
GCLK11
GCLK10
GCLK6or GCLK7or
GCLK10 GCLK11
GCLK5or GCLK4or
GCLK9 GCLK8
GCLK4or GCLK5or
GCLK8 GCLK9
E
D
C
B
GCLK3or GCLK2or
GCLK15 GCLK14
GCLK2or GCLK3or
GCLK14 GCLK15
X1Y1
GCLK1or GCLK0or
GCLK13 GCLK12
X2Y0
GCLK0or GCLK1or
GCLK12 GCLK13
A
X2Y1
Notes:
1. See Quadrant Clock Routing for connectivity details for the eight quadrant clocks.
2. See Figure 45 for specific BUFGMUX locations, and Figure 47 for information on how BUFGMUX elements drive onto a specific clock line
within a quadrant.
The connections for the bottom-edge BUFGMUX elements
are similar to the top-edge connections (see Figure 46).
On the left and right edges, only two clock inputs feed each
pair of BUFGMUX elements.
DS312-2 (v3.8) August 26, 2009
www.xilinx.com
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Product Specification
XILINX [ XILINX, INC ]
