R
Functional Description
Table 69: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued)
Pins/Function
Affected
Values
(default)
Option Name
Description
CRC
Configuration
Enable
Default. Enable CRC checking on the FPGA bitstream. If error detected, FPGA
asserts INIT_B Low and DONE pin stays Low.
Disable
No
Turn off CRC checking.
Persist
SelectMAP
interface pins,
BPI mode,
Slave mode,
Configuration
All BPI and Slave mode configuration pins are available as user-I/O after configuration.
Yes
This option is required for Readback and partial reconfiguration using the SelectMAP
interface. The SelectMAP interface pins (see Slave Parallel Mode) are reserved after
configuration and are not available as user-I/O.
Voltage Supplies
Powering Spartan-3E FPGAs
Like Spartan-3 FPGAs, Spartan-3E FPGAs have multiple
voltage supply inputs, as shown in Table 70. There are two
For additional information, refer to the “Powering Spartan-3
Generation FPGAs” chapter in UG331.
supply inputs for internal logic functions, V
and
CCINT
V
. Each of the four I/O banks has a separate V
CCAUX
CCO
supply input that powers the output buffers within the asso-
ciated I/O bank. All of the V connections to a specific I/O
CCO
bank must be connected and must connect to the same
voltage.
Table 70: Spartan-3E Voltage Supplies
Supply
Nominal Supply
Voltage
Description
Input
V
Internal core supply voltage. Supplies all internal logic functions, such as CLBs,
1.2V
CCINT
block RAM, and multipliers. Input to Power-On Reset (POR) circuit.
V
Auxiliary supply voltage. Supplies Digital Clock Managers (DCMs), differential
drivers, dedicated configuration pins, JTAG interface. Input to Power-On Reset
(POR) circuit.
2.5V
CCAUX
VCCO_0
VCCO_1
Supplies the output buffers in I/O Bank 0, the bank along the top edge of the
FPGA.
Selectable, 3.3V, 2.5V,
1.8, 1.5V, or 1.2V
Supplies the output buffers in I/O Bank 1, the bank along the right edge of the
FPGA. In Byte-Wide Peripheral Interface (BPI) Parallel Flash Mode,
connects to the same voltage as the Flash PROM.
Selectable, 3.3V, 2.5V,
1.8, 1.5V, or 1.2V
VCCO_2
Supplies the output buffers in I/O Bank 2, the bank along the bottom edge of the
FPGA. Connects to the same voltage as the FPGA configuration source. Input
to Power-On Reset (POR) circuit.
Selectable, 3.3V, 2.5V,
1.8, 1.5V, or 1.2V
VCCO_3
Supplies the output buffers in I/O Bank 3, the bank along the left edge of the
FPGA.
Selectable, 3.3V, 2.5V,
1.8, 1.5V, or 1.2V
In a 3.3V-only application, all four V
supplies connect to
Each I/O bank also has an separate, optional input voltage
CCO
3.3V. However, Spartan-3E FPGAs provide the ability to
bridge between different I/O voltages and standards by
reference supply, called V . If the I/O bank includes an I/O
standard that requires a voltage reference such as HSTL or
REF
applying different voltages to the V
inputs of different
SSTL, then all V
pins within the I/O bank must be con-
CCO
REF
banks. Refer to I/O Banking Rules for which I/O standards
nected to the same voltage.
can be intermixed within a single I/O bank.
DS312-2 (v3.8) August 26, 2009
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Product Specification
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