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DS312_09 参数 Datasheet PDF下载

DS312_09图片预览
型号: DS312_09
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- 3E FPGA系列:介绍和订购信息 [Spartan-3E FPGA Family: Introduction and Ordering Information]
分类和应用:
文件页数/大小: 233 页 / 5527 K
品牌: XILINX [ XILINX, INC ]
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Functional Description  
Table 66: Slave Serial Mode Connections  
Pin Name  
FPGA Direction  
Description  
During Configuration  
After Configuration  
User I/O  
HSWAP  
Input  
User I/O Pull-Up Control. When Drive at valid logic level  
Low during configuration, enables throughout configuration.  
pull-up resistors in all I/O pins to  
respective I/O bank V  
input.  
CCO  
0: Pull-up during configuration  
1: No pull-ups  
M[2:0]  
Input  
Mode Select. Selects the FPGA  
configuration mode. See Design  
Considerations for the HSWAP,  
M[2:0], and VS[2:0] Pins.  
M2 = 1, M1 = 1, M0 = 1 Sampled User I/O  
when INIT_B goes High.  
DIN  
Input  
Input  
Data Input.  
Serial data provided by host.  
FPGA captures data on rising  
CCLK edge.  
User I/O  
User I/O  
CCLK  
Configuration Clock. If CCLK  
PCB trace is long or has multiple  
connections, terminate this output  
to maintain signal integrity. See  
CCLK Design Considerations.  
External clock.  
INIT_B  
Open-drain  
Initialization Indicator. Active  
Active during configuration. If  
CRC error detected during  
configuration, FPGA drives  
INIT_B Low.  
User I/O. If unused in the  
application, drive INIT_B  
High.  
bidirectional I/O Low. Goes Low at start of  
configuration during Initialization  
memory clearing process.  
Released at end of memory  
clearing, when mode select pins  
are sampled. In daisy-chain  
applications, this signal requires  
an external 4.7 kΩpull-up resistor  
to VCCO_2.  
DONE  
Open-drain  
FPGA Configuration Done. Low Low indicates that the FPGA is  
Pulled High via external  
pull-up. When High,  
indicates that the FPGA  
successfully configured.  
bidirectional I/O during configuration. Goes High  
when FPGA successfully  
not yet configured.  
completes configuration.  
Requires external 330 Ω pull-up  
resistor to 2.5V.  
PROG_B  
Input  
Program FPGA. Active Low.  
Must be High to allow  
Drive PROG_B Low and  
release to reprogram  
FPGA.  
When asserted Low for 500 ns or configuration to start.  
longer, forces the FPGA to restart  
its configuration process by  
clearing configuration memory  
and resetting the DONE and  
INIT_B pins once PROG_B  
returns High. Recommend  
external 4.7 kΩ pull-up resistor to  
2.5V. Internal pull-up value may  
be weaker (see Table 78). If  
driving externally with a 3.3V  
output, use an open-drain or  
open-collector driver or use a  
current limiting series resistor.  
100  
www.xilinx.com  
DS312-2 (v3.8) August 26, 2009  
Product Specification  
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