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DS312_09 参数 Datasheet PDF下载

DS312_09图片预览
型号: DS312_09
PDF下载: 下载PDF文件 查看货源
内容描述: 的Spartan- 3E FPGA系列:介绍和订购信息 [Spartan-3E FPGA Family: Introduction and Ordering Information]
分类和应用:
文件页数/大小: 233 页 / 5527 K
品牌: XILINX [ XILINX, INC ]
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R
Functional Description  
+1.2V  
+1.2V  
VCCINT  
VCCINT  
P
HSWAP  
VCCO_0  
VCCO_0  
VCCO_2  
HSWAP  
VCCO_0  
VCCO_0  
VCCO_2  
P
VCCO_2  
VCCO_2  
JTAG  
Mode  
JTAG  
Mode  
Spartan-3E  
Spartan-3E  
‘1’  
‘0’  
‘1’  
M2  
M1  
M0  
‘1’  
‘0’  
‘1’  
M2  
M1  
M0  
FPGA  
FPGA  
VCCAUX  
+2.5V  
VCCAUX  
+2.5V  
TDI  
TDO  
TDI  
TDO  
TMS  
TCK  
TMS  
TCK  
PROG_B  
DONE  
PROG_B  
DONE  
GND  
GND  
+2.5V  
JTAG  
TDI  
TMS  
TCK  
TDO  
TMS  
TCK  
DS312-2_56_082009  
Figure 65: JTAG Configuration Mode  
Voltage Compatibility  
JTAG Device ID  
The 2.5V V  
supply powers the JTAG interface. All of  
Each Spartan-3E FPGA array type has a 32-bit device-spe-  
cific JTAG device identifier as shown in Table 67. The lower  
28 bits represent the device vendor (Xilinx) and device iden-  
tifer. The upper four bits, ignored by most tools, represent  
the revision level of the silicon mounted on the printed circuit  
board. Table 67 associates the revision code with a specific  
stepping level.  
CCAUX  
the user I/Os are separately powered by their respective  
VCCO_# supplies.  
When connecting the Spartan-3E JTAG port to a 3.3V inter-  
face, the JTAG input pins must be current-limited to 10 mA  
or less using series resistors. Similarly, the TDO pin is a  
CMOS output powered from +2.5V. The TDO output can  
directly drive a 3.3V input but with reduced noise immunity.  
See XAPP453: The 3.3V Configuration of Spartan-3  
FPGAs for additional information.  
JTAG User ID  
The Spartan-3E JTAG interface also provides the option to  
store a 32-bit User ID, loaded during configuration. The  
User ID value is specified via the UserID configuration bit-  
stream option, shown in Table 69, page 109.  
Table 67: Spartan-3E JTAG Device Identifiers  
4-Bit Revision Code  
28-Bit  
Spartan-3E  
FPGA  
Vendor/Device  
Identifier  
Using JTAG Interface to Communicate to a  
Configured FPGA Design  
Step 0  
0x0  
Step 1  
0x1  
XC3S100E  
XC3S250E  
0x1C 10 093  
0x1C 1A 093  
After the FPGA is configured, using any of the available  
modes, the JTAG interface offers a possible communica-  
0x0  
0x1  
tions  
channel  
to  
internal  
FPGA  
logic.  
The  
BSCAN_SPARTAN3 design primitive provides two private  
JTAG instructions to create an internal boundary scan  
chain.  
0x0  
0x2  
XC3S500E  
XC3S1200E  
XC3S1600E  
0x4  
0x2  
0x2  
0x1C 22 093  
0x1C 2E 093  
0x1C 3A 093  
0x0  
0x1  
0x0  
0x1  
102  
www.xilinx.com  
DS312-2 (v3.8) August 26, 2009  
Product Specification  
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